What does it mean HSE_SWT_RST on S32K311!!!

[enricoantonioli]

Hello all.

Where can I found information about HSE_SWT_RST reset?

With the following clock configuration:

• PLL_PHI0_CLK=120MHz
• CORE_CLK=PLL_PHI0_CLK/1=120MHz
• AIPS_PLAT_CLK=PLL_PHI0_CLK/2=60MHz
• AIPS_SLOW_CLK=PLL_PHI0_CLK/4=30MHz
• HSE_CLK=PLL_PHI0_CLK/1=120MHz
• DCM_CLK=PLL_PHI0_CLK/4=30MHz

at power on I occasionally get the reset HSE_SWT_RST.

What is the cause?

I probably need to reduce the HSE clock to 60 MHz or change the value of HSE_CLK_MODE_AND_GSKT_CTRL to 10 of the dcf_client_utest_misc client.

Where can I find documentation that explains this?

Best regards

E.

[VaneB]

Hi @enricoantonioli 

According to the information, it seems that the problem is due to incorrect clock configuration.

The HSE_CLK_MODE_AND_GSKT_CTRL (bit 30-29) must be set to 1x if you want to use HSE_CLK equal to 120 MHZ. On the other hand, if HSE_CLK_MODE_AND_GSKT_CTRL was set to 00, it is necessary to change HSE_CLK to 60 MHZ. Refer to S32K3xx_DCF_clients file attached to the S32K3xx Reference Manual. 

This must be done by writing to dcf in UTEST memory using Flash controller. You can check the following article, it might be a good reference. 

[S32K3] Restrict the debug access with a password when HSE is not used

BR,VaneB

[enricoantonioli]

HI Vane,

first of all, thank you very much for your quick reply.

At the moment I have reduced the HSE_CLOCK to 60 MHz because in the HSE there isn't programmed a firmware. I will activate HSE soon.

What does HSE_SWT_RST mean? Is it a reset due to an internal HSE watchdog or what? What I don't understand is why this reset occurs if no firmware is programmed into the HSE memory? If I understand correctly, at power on the HSE processor executes the SBAF code and then stops in a WFI. So who triggers the HSE_SWT_RST reset?

Best regards

E.

[VaneB]

Hi @enricoantonioli 

What does HSE_SWT_RST mean? It stands for HSE Software Watchdog Timer Reset.

Is it a reset due to an internal HSE watchdog or what? The HSE CPU is mainly composed of Arm Cortex-M0+, which one of its essential peripherals is the watchdog. 

So yes, it is trigger by HSE SWT as the name implies.

Why this reset occurs if no firmware is programmed into the HSE memory? The HSE CPU, even if the HSE firmware is not loaded, is active because it contains the SBAF code.

[enricoantonioli]

Hi,

Thanks for the precious information, but I still don't understand why in my situation there is a HSE_SWT_RST reset. What is the cause? What's wrong with the HSE?

Best regards

E.

[VaneB · Accepted solution]

Hi @enricoantonioli 

The HSE_SWT_RST is usually caused by wrong clock configuration.

It was found out that it is possible to configure 120MHz HSE_CLK only during reset by DCF record. It cannot be done later by software for some reasons. That means it is necessary to set PLL_ENABLE in BCW (Boot Configuration Word) in IVT, it is necessary to program crystal oscillator configuration flag in UTEST at 0x1B000050 (see section 32.4.3.2 Crystal oscillator configuration flag in the S32K3 RM), it is necessary to program the dcf_client_utest_misc - HSE_CLK_MODE_AND_GSKT_CTRL equal to 10 or 11.