OPWMCB Mode in eMIOS – Lead vs. Trail Edge

[Ayaz]

Hi
I’ve been working with eMIOS PWM IP in OPWMCB mode and wanted to understand the practical difference between these two configurations:

• EMIOS_PWM_IP_MODE_OPWMCB_TRAIL_EDGE
• EMIOS_PWM_IP_MODE_OPWMCB_LEAD_EDGE

To investigate, I created a simple test project and observed the output signals. Surprisingly, I couldn’t see any noticeable difference between the two modes on the waveform.

Here’s my setup:

• Time base: Channel 23
• Channels: CH1 and CH2 generating center-aligned PWM
• The same time base also triggers the ADC at the middle of the period for current sampling.

My questions:

1. What is the actual difference between these two OPWMCB modes?
2. Under what conditions does this difference become visible?
3. For my design (center-aligned PWM with ADC sampling at mid-period), which mode is best and why?

Looking forward to your insights and explanations!

[_Leo_]

Thank you for your interest in our products and for contributing to our community.

Regarding your questions:

1&2 .- The main difference is noted with deadtime insertion. The trail edge mode increasing high time. Alternatively, by selecting the lead edge mode, deadtime insertion decrease high time.

For more details, please refer to 6.4. OPWMCB example project section of S32M27x/S32K3 – eMIOS Usage.

On the other hand, it could also affect the flag event (I don't remember having tried it.), and therefore the interrupt and triggering support.

For reference consult 6.6. PWM design considerations section. And please test it on your own taking as reference the 6.1 OPWMB example project.

3.- Such topic is addressed in https://community.nxp.com/t5/S32K/Design-Strategy-for-Complementary-PWM-Generation-for-motor/td-p/21...

I hope this information is helpful.