MUX_0_CSC only use FIRC clock?

[malove]

Hello,

While referring to the document on generating clocks for the S32K314, I came across a question.

studyseok8466_1-1729556776572.png

[Figure1]

In [Figure1], it states that MUX_0_CSC receives either PLL_PHI0_CLK or FIRC_CLK as its input.

studyseok8466_0-1729556746895.png

[Figure2]

However, in [Figure2], the explanation for the SELCTL bit of MSC_0_CSC only indicates that FIRC can be selected.

So, does this mean that MUX_0_CSC cannot use PLL_PHI0_CLK as a clock source?

[Senlent · Accepted solution]

Hi@studyseok8466

Please refer to latest datasheet , "S32K3xx Reference Manual, Rev. 9, 07/2024".

Senlent_0-1729579325796.png

[malove]

thank you!