Interrupt routing unclear

[abemat]

We would like to enable interrupts on our S32K322 dual core sample. We can trigger interrupts using the generated configuration, but the handler will always be handled by core 0. We would like it to be handled by core 1.

This is a relevant part of the generated configuration:

static const IntCtrl_Ip_IrqConfigType aIrqConfiguration1[] = {
    ...,
    {SIUL_0_IRQn, (boolean)TRUE, 0U},
    ...,
};
const IntCtrl_Ip_CtrlConfigType IntCtrlConfig_0 = {
    128U,
    aIrqConfiguration1 
};
/* List of configurations for routing interrupts */
static const IntCtrl_Ip_IrqRouteConfigType aIrqRouteConfig[] = {
    ...,
    {SIUL_0_IRQn, 3U, undefined_handler},
    ...,
};
/* Configuration structure for interrupt routing */
const IntCtrl_Ip_GlobalRouteConfigType intRouteConfig = {
    128U,
    aIrqRouteConfig
};

And calling the interrupt init from core0:

nxp_status |= (StatusType) IntCtrl_Ip_Init(&IntCtrlConfig_0);
nxp_status |= (StatusType) IntCtrl_Ip_ConfigIrqRouting(&intRouteConfig);
IntCtrl_Ip_InstallHandler(SIUL_0_IRQn, Siul_0_IRQHandler, NULL_PTR);
IntCtrl_Ip_EnableIrq(SIUL_0_IRQn);

When changing the interrupt routing to only be mapped to core 1 (2U), we do not see an interrupt at all anymore. What is the problem here?

/* List of configurations for routing interrupts */
static const IntCtrl_Ip_IrqRouteConfigType aIrqRouteConfig[] = {
    ...,
    {SIUL_0_IRQn, 2U, undefined_handler},
    ...,
};

 @joohau 

[davidtosenovjan]

Hi, could you clarify used environment? Thanks

[abemat]

Does that answer your question @davidtosenovjan 

[davidtosenovjan]

I have agreed with the S32DS expert to answer this question, but we currently have public holidays, so please wait until next week. Thank you for understanding

[winsmen]

Hi! Any update on this issue? @davidtosenovjan 

[abemat]

Hi David, 

We use the S32DS with a Segger J-link. I've debugged it by placing a breakpoint in the interrupt handler and checking from which core it paused in S32DS. We can already use the debugger to step through code on core0 and core1, so we know that it recognizes the cores separately.

[jiri_kral]

Hi, 

I'm not much familiar with the RTD and S32K3xx - but it looks, that there is not properly setup the platform package - if you like to handle some IRQ only by core 1, you need to uncheck core 0 (image is only for reference, the project is only single core - in your case the Core 1 column should be available for editing): 

Jiri

[winsmen]

@jiri_kral I did uncheck core0 and set only core1 as the target of the interrupts I would like to be serviced only on core1, but with this configuration the ISRs never get called. However, I do see the flags from the peripherals which are meant to trigger the ISRs being set.