Hi
AN12522 states about ECC RAM:
- 2.2 Used ECC algorithm
The ECC implementation for the SRAM uses a Modified Hamming Code scheme with 40-bit check base that consists of 32-bits of data plus 8-parity bits.
Clearly RAM initialization should be done in 32-bits aligned word writes. I thought that initializing RAM writing byte by byte could easily trigger ECC error flags set in ERM (I'm using S32K144 and S32K148). But S32DS startup code indeed seems initializing RAM byte by byte:
uint8_t * data_ram;
uint8_t * code_ram;
uint8_t * bss_start;
...
/* Copy initialized data from ROM to RAM */
while (data_rom_end != data_rom)
{
*data_ram = *data_rom;
data_ram++;
data_rom++;
}
/* Copy functions from ROM to RAM */
while (code_rom_end != code_rom)
{
*code_ram = *code_rom;
code_ram++;
code_rom++;
}
/* Clear the zero-initialized data section */
while(bss_end != bss_start)
{
*bss_start = 0;
bss_start++;
}
Since it is told that out of power on SRAM isn't initialized and ECC bits are most likely not OK, I decided to check it. Cloning flash Debug configuration and making debugger not reload flash but connect without reset to running MCU, powering MCU down for a while, then powering on, connecting debugger and inspecting ERM status registers I found that indeed status bits do report ECC problems. Then I added loop code into startup_S32K144.S to step through the rest of startup and figuring out what actually triggers ECC flags. ECC errors start flipping from the first byte by byte initialization loop.
My question are here. "Modified Hamming Code scheme with 40-bit check base that consists of 32-bits of data plus 8-parity bits.". Does it mean that 1) every RAM byte has dedicated 8/4=2 ECC bits? 2) Is it safe to write just single byte to uninitialized RAM DWORD and expect to read the same byte value after writing remaining 3 bytes of the same RAM DWORD?
Thanks
Edward
