Hello Vlad,
Sorry for the late response.
There are three clocks.
LPSPI bus interface clock is always BUS CLK gated by PCC module, see Table 27-8 RM rev12.1.
BUS CLK can be max 56MHz in HSRUN.
Peripheral functional clock is also configurable in PCC[PCS]. The frequency must be less or equal to BUS CLK.
Then in LPSPI module the functional frequency (56MHz) is divided using a prescaler in LPSPI[TCR] register. If set to 0, it divides the functional clock by 1 (56MHz).
The SPI bit rate is set by SCK divider in LPSPI[CCR] register. The division factor is equal to SCKDIV + 2. It means the bit rate can be set theoretically to 28MHz.
But as you can see in S32K DS the bit rate is limited to 14MHz in HSRUN in order to sample data coming from a slave.
Using Master loopback feature (CFGR1[SAMPLE]) which delays SCK clock for sampling the slave data, the bit rate can be set up to 24MHz provided the MCU runs at 5V power supply.
If you can set only 4MHz, you probably set something wrong. Please check all the registers mentioned above. And make sure the MCU is in HSRUN, if you use it.
Regards,
Daniel