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S32K1xx   S32K144 Example S32K144 CMP Round-robin S32DS2.0  Example S32K144 Verify Backdoor Access Key S32DS1.3  Example S32K144 FlexCAN0 RXFIFO DMA nonSDK S32DS13  Example S32K144 PDB ADC trigger DMA ISR S32DS  Example S32K144 Flash RW simple S32DS  Example S32K144 DMA memory copy test S32DS  Example S32K144 EEEPROM usage Example S32K144 EEEPROM usage - No SDK  Example S32K144 RTC VLPS  Example S32K144 WDOG RCM interrupt  Example S32K144 SRAM ECC Injection  Example S32K144 RAM Retention S32DS.R1 Example S32K144 I2C Master MPL3115A2 S32DSR1_v3  Example S32K144 FlexCAN RXFIFO DMA S32DS.ARM.2018.R1  Example S32K144_printf_implementation - S32DS_1.0  Example S32k144 UART printf/scanf under FreeRTOS - S32DS Example S32K144 SDK Function call on configurable period using LPIT timer.  Example S32K144 .noinit section usage Example S32K144 PDB ADC DMA S32DS.ARM.2018.R1   Example S32K144 RAM selftest simple S32DS 2018.R1  Example S32K144 Position Independent Code  Example S32K144 FlexCAN Pretended Networking STOP mode test S32DS.ARM.2.2  Example S32K144 LPIT DMA LPSPI  Example S32K144 FlexCAN TX/RX/Error ISR test S32DS2.2  Example S32K144 FlexIO Idle Detection S32DS2.2   S32K142 Example_S32K142_LMEN_Cache_v1_0_S32DS3.6_RTD300  Lauterbach_Script_For_MDM_AP_Mass_erase_S32K142    S32K146 Example S32K146 Set_whole_FlexRAM-as_RAM S32DS.ARM.2.2   S32K148 Example S32K148 PDB0-PDB1 ring S32DS3.4 RTM4.0.3  Example S32K148 PDB0-PDB1 ring DMA S32DS3.4 RTM4.0.3  Example S32K148 GPIO Interrupt     S32K116 Example S32K116 WDOG Fast Test  Example S32K116 LPUART LIN Slave TXRX ISR S32DS.ARM.2.2  Example S32K116 FlexCAN PN STOP S32DS.ARM.2.2 Example S32K116 FlexCAN VLPR test S32DS.ARM.2.2   S32K118 Example S32K118-SRAM-keep_data_over_SW_reset v0_1 S32DS.ARM.2.2   S32K3xx   S32K312 Example S32K312 ADC_IP Continuous Scan DMA S32DS36 RTD600    S32K344 Example S32K344 PIT BTCU ADC DMA DS3.4 RTD100   Example S32K344 FlexCAN_Ip TX/RX/EnhanceRXFIFO test S32DS3.4 RTD200     Example Siul2_Port_Ip_Example_S32K344_ITCM_DTCM S32DS3.4 RTD300   Example S32K344 LPUART RX/TX ISR FreeRTOS S32DS36 RTD600    Example_S32K344_MCAL_MCU_ClockMonitor_v1_0_S32DS36_RTD600    Example_S32K314_DTCM1_Backdoor_RTD201_DS34_v3    Example_Reg_Prot_Flash_Controller_S32K344   Example S32K344 PIT SWtrig ADC ANAMUX S32DS 3.6.0 RTD 6.0.0   Example S32K344 EMAC lwIP FreeRTOS miniEVB S32DS 3.6.1 RTD 6.0.0   Example S32K344 EMAC lwIP FreeRTOS MRCANHUB S32DS 3.6.1 RTD600   Example_S32K344_BIST_eMCEM_SPD106_v2_0_S32DS365_RTD700  Example S32K344EVB_T172 UART_ETH_Gateway HLD S32DS368 RTD701   Example_S32K344_CMU_FM_POR_WDG_v1_0_S32DS369_RTD701    Example_S32K344_FLS_Integrity_Margin_Check_v1_0_S32DS36_RTD701    S32K358 Example S32K358 FlexCAN TXRX ISR S32DS35 RTD400/500   Example S32K358 GMAC 100M lwIP FreeRTOS S32DS 3.6.1 RTD600   Example S32K358 GMAC 1G lwIP FreeRTOS S32DS 3.6.1 RTD600   Example S32K358 GMAC lwIP FreeRTOS RDBESS S32DS 3.6.1 RTD600   Example_S32K358_XRDC_SEMA42_Multicore_v1_0_S32DS369_RTD701    S32K388 Example S32K388 GMAC0 lwIP FreeRTOS S32DS 3.6.1 RTD600   S32K389 Example S32K389 GMAC0 lwIP FreeRTOS S32DS 3.6.1 RTD 6.0.0   Example S32K389 GMAC1 SABRE lwIP FreeRTOS S32DS 3.6.1 RTD600  
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******************************************************************************************** * Detailed Description: * LPIT_ch0 triggers DMA_ch0 periodically (1ms). * Every trigger starts a minor DMA loop (8 bytes) transfer to the LPSPI1 TX FIFO. * There are 8 minor loops per one major loop (64 bytes in 8ms). * LPSPI1 sends two 32bit frames every 1ms. * LPSPI1 RX data are masked, they are not stored in the RX FIFO. * ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: S32K144 0N57U * Debugger: S32DS 2.2, OpenSDA * Target: internal_FLASH ********************************************************************************************
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******************************************************************************************************** Detailed Description: On WDOG timeout, the WDOG module requests reset in the Reset Control Module (RCM). The reset request to RCM can be delayed by 128 bus clock cycles if the WDOG interrupt is enabled (WDOG_CS[INT] = 1). If enabled, the WDOG interrupt vector is fetched or it becomes pending in NVIC. After the delay, the reset is requested in RCM. Independently of the WDOG interrupt, the RCM can again delay the reset by up to 514 LPO additional clock cycles if the corresponding RCM_WDOG interrupt is enabled (RCM_SRIE[GIE, WDOG] = 1). If so, instead of forcing reset immediately, the module requests the RCM interrupt in NVIC and forces the reset after the additional delay (RCM_SRIE[DELAY]). Either way, the reset is forced, it can’t be stopped only delayed. This example enables the WDOG interrupt in the WDOG_CS register but leaves this interrupt disabled in NVIC. That means that this interrupt becomes pending in NVIC on the WDOG timeout, it sets the WDOG_CS_FLG, but the vector doesn’t get fetched. The RCM interrupt is enabled and it gets asserted in NVIC after the WDOG interrupt delay (2.67us (48MHz BUS CLK)). The WDOG flag (WDOG_CS_FLG) is read in the RCM ISR instead. The execution stays in an infinite loop for 514 LPO (128kHz) cycles (~ 4ms) until the reset is forced. ------------------------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 OpenSDA Target: internal_FLASH ********************************************************************************************************
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********************************************************************************  Detailed Description:  Example shows how to use FlexCAN 0 Pretended networking mode to allow FlexCAN  module to wake up MCU from STOP mode.  Wake up by Timeout and wake up by Match events are enabled.  Also pin interrupt can be used to exit STOP mode.  So MCU enters STOP mode by pressing SW3 button.  MCU exits STOP mode when one of following happens:  - no CAN message comes in 8sec (CAN PN timeout event)  - message with standard ID 0x554 or 0x555 comes (CAN PN match event)  - SW2 button is pressed (PTC12 interrupt)  In run mode blue LED is dimming and the rate is different for each wakeup event  ------------------------------------------------------------------------------  Test HW: S32K144 EVB-Q100  MCU: FS32K144UAVLL 0N57U  Fsys: 160MHz  Debugger: Lauterbach, OpenSDA  Target: internal_FLASH ********************************************************************************
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****************************************************************************************************************** Detailed Description: The example code shows CMP in Round-robin mode. CMP is clocked (125kHz) and triggered (80ms) by LPTMR, operates in VLPS. Input channels are CMP0_IN1 (PTA1), CMP0_IN2 (PTC4), CMP0_IN3 (PTE8), CMP0_IN4 (PTC3). The initial state of CMP outputs is 0 (Input analog pins < DAC input (Vin1/2)) The input pins are pulled down internally for debugging purposes. CPM will wake up the MCU if an input has changed. BLUE LED flashes 1x if CMP_IN1 has changed, 2x CMP0_IN2, 3x CMP0_IN3, 4x CMP0_IN4. After that, the MCU goes back to VLPS. ------------------------------------------------------------------------------------------------------------------------------------- Test HW: S32144EVB-Q100X MCU: S32K144 (0N47T) Debugger: S32DS2.0, OpenSDA Target: internal_FLASH ******************************************************************************************************************
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