Hello @ARM_Kami,
Thanks a lot for the information. I was checking the guide you referenced and I see the suggested changes in some registers you have modified in the QSPI parameters you just sent. However, there are some registers I did not see mentioned in the guide but were modified:
I notices that this register was mentioned in a Linux related patch, for BSP30, my understanding is that it does not need to be changed for the QSPI parameters used for Boot ROM.
For the following registers, can you provide more information as why you changed them? since I cannot access the memory documentation.
Also, have you checked the QSPI lines in the board with an oscilloscope? if so, can you share the signals you see in the QSPI lines or if you don't see anything at all?
Thanks in advance for the information.
Hi Alejandro,
I created the file for the QSPI config based on info from the SoM provider, they use a similar config to boot Yocto based system, (by similar I mean they don't use the nxp IDE to program their system).
When I saw the resulting file, this was the same as the one in the reference I quote.
the note about "However, there are some registers I did not see mentioned in the guide but were modified":
In the NXP ide the setting as you saw them are:
As I mentioned it ia custom board, using a SoM, I don't have the option to instrument it to get the requested signals.
About the " For the following registers, can you provide more information as why you changed them? since I cannot access the memory documentation. " => The changes I did were based on the info from the SoM provider.
And they are the same as in the quoted ref.:
The QSPI config. are confirmed to work in a linux system.
The 500 ms timeout doesn't seem to be a problem for the code size loaded in SRAM (2.6Mb).
Do we have a way to confirm that the code is completed loaded? a flag to confirm?
Do we have further contrains about the use of NOR Flash loading to SRAM when using Ethernet, SPI, FreeRTOS?
If only the QSPI config. is the key for being able to boot from NOR Flash please provide further support.
Regards,
Hello @ARM_Kami,
I think there might be a confusion, I was asking why the change in the registers: MDIS, PPWB, TPADA1 and TPADA2, since I don't see those registers mentioned in the guide (1399906). I checked your binary in S32DS and saw the changes. To reduce the problem, please share the following information:
- RCON word value
- Are you using parallel RCON (dip switches) or serial RCON (EEPROM memory)?
- I understand you obtained your board from a manufacturer, what is the brand and model of the board?
- With your last message I understand that the register configuration and the LUT sequence you are using have been tested with Linux during runtime, is that correct?
- Comparing one of the available configurations with yours I notices that de padded part is in 0xFF in yours and it is 0x00 in one of the provided by us, on the right is your configuration and on the left is one of the available after isntalling S32DS:
- Did you changed this deliberately?
- When you use the flash tool, what is the result?
- To check if the chip is loading the full image in less than 500ms you can perform some tests:
- You can monitor the RESET_B pin with an oscilloscope and check the waveform
- You can compile a simple application, like a Blink LED, flash it and check if the behavior changes.
- You can monitor the consumption of the board and compare it with the configuration you know are working, like SD card.
Let me know if you find this information useful and please share the results of the tests in case you are able to perform them.
Thanks
