SPLL_CLK can not selected as SCS_CLK
‎07-02-2020
02:29 AM
912 Views
s8113595
Contributor I
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
S32 Design Studio for ARM
Cpu:S32K116_48
S32_SDK_S32K1xx_RTM_3.0.0
use clock_manager
my problem is:
as in the following picture,I can't select SPLL_CLK as SCS_CLK.
who can help me,think you!
1 Reply
‎07-02-2020
03:49 AM
847 Views

NXP TechSupport
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
Unfortunately, the Phase-locked loop (PLL) is not available for the S32K11x product series. That is why you cannot select it.
Please, refer to the Reference Manual rev 12.1 "Figure 27-1. Clocking diagram" note number 3.
" 3. For S32K11x, inputs and muxes connected to PCC are Reserved. Also SPLLDIVx_CLK are Reserved as indicated in RED "
Best regards,
Diana
