Hi Kim,
Yes, your understanding is correct.
The debugger cannot expect asynchronous COP reset. When the reset is not directly triggered by the debugger, the BDM connection is lost and clocks with registers are revert back to the default values during reset sequence.
If you want to test the COP reset behavior, please do it in normal mode (without debugger).
Instead of LEDs, you may use for example SCI channels or any other way for signalization…
Note: You should use just one definition for COP reset vector. If you will define COP reset vector like “interrupt 2 void COP_ISR(void)”, you should comment out definition in prm linker file “//VECTOR 2 _Startup”.
Please check capacitance on the RESET pin.
For example: The DEMO9S12XHY256 board has 100nF capacitor at RESET pin and 10KOhm external pull-up. The board is assembled by the 8MHz crystal.
If we omit internal pull-up and internal capacitance of RESET pin, the time constant t=R*C is 1ms. In this case, the POR reset vector is always used for all type of resets.
The RESET pin is tested after 64 SYSCLK cycles from RESET pin release. For MCU reset, the SYSCLK=OSCCLK. So, it presets 8us time window where the voltage at reset pin should reach a high level which is necessary for correct COP/CM reset source recognition. If we stay with 10kOhm pull-up, the maximum capacitor value at RESET pin should be below approximately 800pF.
Note: Optionally, you may connect reset button and capacitor to the RESET pin through a Schottky diode. In that case, the capacitor will be not discharged by a system reset like COP or CM.
I hope it helps you.
Have a great day,
Radek
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