Hi 刘 银
I am slightly confused from your CS(SS) bit configuration. The SPI0CR1 and SPI0CR2 configuration specifies, that SS pin is driven by SPI module. While CS_D=ON; commands looks like manual driven SS pin.
Anyway, you selected CPOL=0 and CPHA=0. In that case, bytes (or words if XFRW=1) must by divided by SS pin line toggling (SS line is always deasserted and reasserted between successive transfers for at least minimum idle time)
So, if you use manual driven SS, you must toggle SS pin twice between bytes.
Possible solutions:if
1. If you use manual driven SS, add code for SS pin toggle between byte transfers.
2. Use SS pin signal generated by SPI module
3. Use CPOL=1, CPHA=1 configuration (SPI Mode 3 per FM25640 datasheet)
Important note:
Please be aware, that while(!SPI0SR_SPIF); command cannot be debugged in stepping mode. The SPIF flag is cleared by read SPISR register with SPIF == 1 and then read SPIDRL register. That reading is applied also by debugger when you step over code – debugger clears SPIF flag by register reading when CPU halt.
I hope it helps you.
Have a great day,
Radek
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