RAM over flow issue

[satishperumal]

Hi ALL,

i am new to this embedded feild , i am facing an issue with my system,

i am using HCs12 compiler , microcontroller : MC9s12xEq512x

i believe my system is malfunctioning in run time and Recovers back after some time and sometime only after POWER RESET(battery OFF/ON). when i am tracing with help of CAN , i can see some values goes to maximum  , i am using array , in run time that array values goes to high during malfunction. and also recovers back.

consider i am using data as follows:

FI = ECT_1;

in run time i can see my ECT_1 is fine, and it did get affected, but FI is showing some random value, when i am seeing the Variable in memory window(with help of BDM), i can see it is getting overwritten by some other value.

In my linker i see Default: RAM, RAM_FD, RAM_FC.

RAM is non paged RAM, RAM_FD, RAM_FC are paged RAM. some global variables are in RAM_FD, RAM_FC is Free. we have created #pragma in RAM_F8, but i can see many of my  variables are in RAM_FD, under the SEGMENT RAM_FD_133, in map file i am able to see RAM_FD_133 is creeted sequentially after PAGE_132 and before PAGE_134.

i doubt my variable in this Segment RAM_FD_133 is getting overwrriten in Run time.

i tried reproducing this scenario in compile time, i just increased my Stack size from 1K to 2K, many variable goes to high values and system behaves abnormal in this point of time. i have attached my map file and linker files for reference, please help me out.

thanks in Advance.

Original Attachment has been moved to: GoodBoy.map.zip

Original Attachment has been moved to: LinkerPRM_CCP.prm.zip

[kef]

Like in case with your competitor here

https://community.freescale.com/thread/300659

your problem is

      .stack,                 /* allocate stack first to avoid overwriting variables */

      SHARED_DATA,            /* variables that are shared between CPU12 and XGATE */

      DEFAULT_RAM             /* all variables, the default RAM location */

                        INTO  RAM,RAM_FD,RAM_FC;

Bold italic part has to be not present ^^ here. You won't solve anything until you remove these. Of course linker may start complaining about no space in RAM. You should see thread above, CW technical notes, also use community search to find how to solve this.

[satishperumal]

Thanks for your Reply Mr. Edward,

in this case if i remove all the Paged RAM from Default RAM, i ll be in need of huge RAM area for for my variables, if i push all my variables into Paged RAM using #pragma and assigning the DATA_SEG to that Particular Paged RAM,

should i assign the paged_RAM which i am using any where in linker,

anywhere else Assigning the Data_SEG to paged RAM_FC

for example,

/*******************************************************/

#pragma DATA_SEG DATA1

//variables

#pragma DEFAULT

/***************************************************/

in LInker

DATA1 into RAM_FC,

/***************************************************/

or should i assign my RAM pages to anywhere in linker, or else my data will be fetched from paged rram in Run time automatically.

thanks in advance

[kef]

• i ll be in need of huge RAM area

What do you really mean here? Do you have a lot of small objects or few big ones that don't fit 4k RAM page?

I think all your questions are already answered in these forums. Just follow above mentioned thread and url's provided in my older post, also use community search. If you have particular problem with allocating or accessing your object, then direct way to get help is to provide exact piece of code that shows the problem.

[satishperumal]

from  your post and thread you posted, can i come to an conlcusion, moving all the variable from non paged ram to paged RAM using the paging technique.so that my Non paged RAM will be free and in run time ,it will be free to access stack and non paged RAM ?.

[kef · Accepted solution]

Paged RAM is slower to use, so it doesn't make sense to me to move all variables to paged RAM. It is also not clear why do you want to keep nonpaged RAM free?

It is the best to allocate all variable objects (and of course stack) to nonpaged RAM. When they all don't fit in nonpaged RAM, you move some less used, not performance critical, not used by ISR variables to paged RAM.

[satishperumal]

thanks for your Reply mR. edward... your answer is very helpful for me to understand the issue.. thanbks once again