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Problem installing 2nd CD of Freescale Linux SDK for QorlQ Processor

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T1024 10G port not consistently up

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about DDR3L power supplying

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We are using LS1043A, in that SerDes Lane A as configured as XFI and routed through a backplane to another Daughter card(same board works for Redundant purpose in our system) where the destination is also LS1043A.

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I'm using LS1043A in my design, and we are not using QE in our board. In RCW what should i Set for bit 166(HDLC1_MODE) and 167(HDLC2_MODE)?

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We are using LS1043A in our design, In which four devices are connected to IFC, which are 256MB NOR Flash, 2GB NAND flash, CPLD and FPGA.

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I'm using LS1043A, In that IIC2 pins are muxed with the SDHC_CD_B and SDHC_WP.

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We are using LS1043A, in that we are using both EC1 and EC2.

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LS1021A. Switch from secure to non-secure

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We are using LS1043A in our System. I need to Set the RCW configuration for MEM_PLL_RAT(10-15)

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4 Replies 1359 Views

QorIQ

Discussions

Problem installing 2nd CD of Freescale Linux SDK for QorlQ Processor

T1024 10G port not consistently up

about DDR3L power supplying

We are using LS1043A, in that SerDes Lane A as configured as XFI and routed through a backplane to another Daughter card(same board works for Redundant purpose in our system) where the destination is also LS1043A.

I'm using LS1043A in my design, and we are not using QE in our board. In RCW what should i Set for bit 166(HDLC1_MODE) and 167(HDLC2_MODE)?

We are using LS1043A in our design, In which four devices are connected to IFC, which are 256MB NOR Flash, 2GB NAND flash, CPLD and FPGA.

I'm using LS1043A, In that IIC2 pins are muxed with the SDHC_CD_B and SDHC_WP.

We are using LS1043A, in that we are using both EC1 and EC2.

LS1021A. Switch from secure to non-secure

We are using LS1043A in our System. I need to Set the RCW configuration for MEM_PLL_RAT(10-15)

IEEE1588 Implementation in DPDK on DPAA2 Platforms

Configuring LS1021A in USB Gadget mode

Inter-core Communication Application Development Based on OpenIL Baremetal Framework

Ethernet Flow Control Configuration in DPDK on LS1043A Platform

EDAC L1 and L2 cache error detection and correction on LS1043