I have doubt in setting RCW value for bits MEM_PLL_RAT(10-15) which is used to select DDR Clock. In datasheet in table 159 it is mentioned as the ratio between DDR datarate: DDRCLK ratio, but in Reference Manual It is mentioned as the ratio between DDR PLL:SYSCLK Ratio.
My Core Freq is 1.6GHz, Platform Freq is 400MHz, and DDR Data rate need to 1600MT/s. Kindly help me what value should i keep in MEM_PLL_RAT(10-15) RCW setting?