local memory Map for MPC8358E processor

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local memory Map for MPC8358E processor

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venkat1
Contributor III

Hi Folks

We are using MPC8358E processor and we configured the local memory as shown in the fig.. mainly we are struggling with DDR interface. so please confirm this memory mapping.

is this DDR memory mapping is right?

venkat1_1-1602481094362.png

Regards,

Venkat

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ufedor
NXP Employee
NXP Employee

Please refer to the MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, 4.4.3 System Clock Domains:

"The internal ddr_clk frequency (for DDR) is determined by RCWL[DDRCM]. Note that the lb_clk clock
frequency (for Secondary DDR) is determined by RCWL[LBCM]. See Section 4.3.2.1, “Reset
Configuration Word Low Register (RCWLR).” Note that ddr_clk is not the external memory bus
frequency; ddr_clk passes through the DDR clock divider (÷2) to create the differential DDR memory bus
clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk."

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ufedor
NXP Employee
NXP Employee

Proposed memory map is incorrect.

Please read the MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, 5.2 Local Memory Map Overview and Example

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venkat1
Contributor III

Thank you for replying,

As per MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual says, we can put  boot flash on All zeros address or 0xFF80_0000 address. can you please elaborate more on this?.  so that, my memory mapping is incorrect...

Regards,

Venkat

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ufedor
NXP Employee
NXP Employee

What is the DDR SDRAM size?

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venkat1
Contributor III

DDR size-64MB

Manfr- micron

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ufedor
NXP Employee
NXP Employee

What are RCWLR and RCWHR values?

 

 You wrote:

> we are struggling with DDR interface

What does it mean?

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venkat1
Contributor III

RCWLR- 0x02230086

RCWHR- 0x00600000

 

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ufedor
NXP Employee
NXP Employee

You wrote:

> we are struggling with DDR interface

What does it mean?

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venkat1
Contributor III

 

#RCWLR Value :- 0x02230086

#LBCM-0   LBCM is equal to csb clk (266MHz)

#DDRCM-0  DDRCM is equal to csb clk (266MHz)

#SVCOD-00  system PLL VCO division is 4

#SPMF - 0010 system PLL multiplication factor is 2:1

#COREPLL -0100011 Core freq.  1600MHZ 

#CEVCOD -10 QUIIC engine Freq. is 800MHZ

#CEPDF - 0  QUIIC Engine PLL div. factor is 0

#CEPMF- 00110 QUICC engine PLL mortification factor 6

 

#RCWHR Value :- 0x00600000

#PCIHOST-0   PCI is disable (not using)

#PCIARB-0  PCI arbiter is disable

#PCICKDRV - 0 PCI Buffers are disable

#COEDIS- 0 core can boot without waiting for config. by external master

#BMS- 0 boot memory space is all zeros to 0x007f_ffff

#BOOTSEQ- 00 boot sequencer disabled

#SWEN - 0 Software WDT disable

#ROMLOC- 110 local bus GPCM 16-bit ROM

#SDDRIOE -0 secondary DDR I/O disable

#TLE -0 big-endian mode

#LALE - 0 normal LALE timing 

#LDP-0 initial value  of SCIRL[LDP_A] is 1 means that LDP0-LDP3 are used for local data parity

 

 

 

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venkat1
Contributor III

And please find the attached document of my init file 

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ufedor
NXP Employee
NXP Employee

You wrote:

> we are struggling with DDR interface

What does it mean?

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5,330 Views
venkat1
Contributor III

> we are struggling with DDR interface

>What does it mean?

I am not able to access DDR memory. and DDR doesn't  responding to the configured address. 

 

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ufedor
NXP Employee
NXP Employee

There are two possibilities:

1) DDR SDRAM connection is incorrect

2) DDR controller initialization settings are incorrect.

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venkat1
Contributor III

There is no doubt in DDR SDRAM hardware part.

I am not sure about DDR controller initialization settings..

PFA of DDR controller initialization file 

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ufedor
NXP Employee
NXP Employee

Please provide:

1) DDR SDRAM connection schematics as searchable PDF

2) what is measured frequency of the MCK?

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venkat1
Contributor III

PFA of DDR SDRAM interface Schematic

&

MCK frequency is 133MHZ

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venkat1
Contributor III

@ufedor  are u there?

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venkat1
Contributor III

sir,

can we control DDR  operating frequecy(MCK)? if it is yes!  How?

 

 

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ufedor
NXP Employee
NXP Employee

Please refer to the MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, 4.4.3 System Clock Domains:

"The internal ddr_clk frequency (for DDR) is determined by RCWL[DDRCM]. Note that the lb_clk clock
frequency (for Secondary DDR) is determined by RCWL[LBCM]. See Section 4.3.2.1, “Reset
Configuration Word Low Register (RCWLR).” Note that ddr_clk is not the external memory bus
frequency; ddr_clk passes through the DDR clock divider (÷2) to create the differential DDR memory bus
clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk."

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