P1010 Ethernet controller reading PHY register value error

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

P1010 Ethernet controller reading PHY register value error

1,521 次查看
Makabaka
Contributor II
Dears: I used the P1010(one MAC) to connect the 7 Ethernet PHYs(88E548) via the conversion chip, and then each PHY chip had four Gigabit ports, for a total of 28 Gigabit PHYS. When I set the PHY address from 0x04 to 0x1F, the P1010 MDIO correctly reads all the PHY registers value except for the address 0x1E's PHY. When I set the PHY address from 0x00 to 0x1B, the P1010 MDIO correctly reads all of the PHY's registers. Now the PHY address 0x00 to 0x03 is occupied by other ETH ports, so it can only be set to 0x04 to 0x1F. Please give some suggestion how to modify it to correctly read the PHY register value with address 0x1E. From now on , Changed the TBIPA register value of the P1010 from the default value of 30 to 29. The problem still exists. Thanks
0 项奖励
回复
3 回复数

1,503 次查看
Makabaka
Contributor II

Hi Ufedor:

Yes, At most 31 external PHY can be addressed, And I just used 28 external PHY. 

May I changed the  TBI PHY address to other value? such as: one of 0x00/0x01/0x02/0x03.

Thanks  

 

0 项奖励
回复

1,500 次查看
ufedor
NXP Employee
NXP Employee

> May I changed the TBI PHY address to other value? such as: one of 0x00/0x01/0x02/0x03.

Yes.

0 项奖励
回复

1,513 次查看
ufedor
NXP Employee
NXP Employee

Please refer to the P1010 QorIQ Integrated Processor Reference Manual, 15.7.6 MII management address register (eTSEC_MDIOx_MIIMADD):

"PHY_Address

At most, 31 external PHYs can be addressed, because one of the 32 possible addresses this field can hold is reserved for the TBI (internal PHY)."

0 项奖励
回复