strange behaviour with chip select bounds on DDR controllers

[frankdischner]

Hello,

I'm working with the P4080DS and trying to configure the two DDR controllers to access the same memory space but without interleaving. I have one LAW configured with address 0x00000000 and size of 1GB assigned to DDR controller 1 and a second LAW with address 0x40000000, 1GB and assigned to DDR controller 2. This works fine and I can access all 2GB of RAM, however, I want the second gigabyte to address the same physical RAM as the first gigabyte. In other words, I want both controllers to always use cs0 and never cs1. No matter how I configure the cs bounds, I always read 0xdeadbeef (the initialization value) from addresses above 0x40000000 so it seems that the second controller is always using cs1. If I configure only a single LAW with size 2GB to a single controller (doesn't matter which one) and cs0 bounds to 0x00-0x7f, then I see the memory mirrored as I expect. Also, if I use a single controller with cs0 bounds 0x00-0x3f and cs1 bounds 0x40-0x7f, then I can access the entire 2GB of physical memory. It's only when I have both controllers enabled that the chip select bounds seem to be ignored. Any idea what I might be doing wrong?

Thanks

-Frank

[Bulat]

Your description is not so clear, probably you can explain the problem better? For example, "I want the second gigabyte to address the same physical RAM as the first gigabyte" sounds very doubtful, like you are going to address the DIMM connected to the DDRC1 from the DDRC2.

It would be helpful if you listed settings of the registers like BNDS, CONFIG, SDRAM_CFG and explain what you expected to get and what you really got.

Regards,

Bulat

[frankdischner]

Hi Bulat,

Your description is not so clear, probably you can explain the problem better? For example, "I want the second gigabyte to address the same physical RAM as the first gigabyte" sounds very doubtful, like you are going to address the DIMM connected to the DDRC1 from the DDRC2.

Yes, this is what I was looking to do, but maybe it's not possible. I was under the impression that both controllers were somehow connected to both DIMMs, but your response suggests that each controller is connected to only one DIMM. Can you confirm that this is the case? Is there some documentation, schematic, or diagram somewhere that describes this? I was unable to find anything concrete. This is on the P4080DS revision 3.

Thanks,

-Frank

[Bulat · Accepted solution]

DDR controllers are absolutely independent from each other. This means that each controller has its own memory bus interface including address, command, control signals, allowing to connect up to two dual-rank DIMMs. Or in other words each controller can access only SDRAM devices connected to its bus interface. In particular this means also that  CS0 and CS1 signals/pins of the first DDR controller are physically different of CS0 and CS1 signals/pins of the second one (referred to as D1_CS0, D1_CS1 and D2_CS0, D2_CS1) so they physically can not address the same memory device.

Probably figure 1-1 of the Ref Manual  (Block Diagram) is helpful.

Regards,

Bulat