RF LDMOS MMRF2010 gate-source current at operative bias

[Sedorf]

From document MMRF2010N Rev. 1, 04/2017 pag.3 we read Vgs1= 7.0V @ Idq1= 80mA and Vgs2= 2.7V @ Idq2= 150mA. Across resistors R1, R2 (3.9k on stage#2, 1k on stage#1 see pag.6) you connect same potential Vbias for stages.. what is this potential in Volt, or equivalent, what is the amount of gate-source currents (Igs1, Igs2) on this working conditions of polarization?

[diazmarin09]

Hello Sedorf,

Please accept my apologies for the delayed response.

I am afraid that I do not have such data characterized, but I have already requested further information.

In case I receive some data I will contact you immediately.

Regards,

David

[diazmarin09]

Hello Sedorf,

Thank you for your patience, please review the information below:

We do not recommend that the same potential be placed at R1 and R2, the transistor will not be properly biased per the datasheet.  Igs1 and Igs2 are typically very low…less than 1mA. Some of the current from the gate is being drawn be the temperature compensation circuit.

The over temp compensation typically needs a greater slope for the second stage device. If R1=R2=1Kohms and the same gate potential is applied to both gate feed networks, the driver will be under biased and result in a large amount of gain expansion on drive up.

Example

If R1=R2=1Kohms,

And Vgs1=Vgs2=2.5V  with Vdd=50V  Then Ids1=7mA, Ids2=150mA, Igs1=240uA, Igs2=200uA (lower gain, Large gain expansion)

Proper bias if R1=R2=1Kohms would be:

Vgs1=4.7V, Vgs2=2.5V  with Vdd=50V  Then Ids1=78mA, Ids2=150mA, Igs1=400uA, Igs2=200uA

Non optimal R1=R2=1Kohms  (large gain expansion)

Vgs1=2.7V, Vgs2=2.7V  with Vdd=50V  Then Ids1=12mA, Ids2=253mA, Igs1=270uA, Igs2=220uA

I hope this information helps.

Regards,

David

[Sedorf]

TNX David, excuse for late.

So, you assert the proper bias condition for stages both supplied with 1k resistor is:

Vgs1= 4.7V Igs1= 400uA to obtain Ids1= 78mA

Vgs2= 2.5V Igs2= 200uA to obtain Ids2= 150mA

Are experimentals data?

To improvement the stability on temperature range of stage#2, is  wise to bring the gate-resistor from 1k to 4k?