Problem with Event Status Registers of the uja1169 chip

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Problem with Event Status Registers of the uja1169 chip

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Baikian
Contributor II

I am currently using the 1169 SBC and have encountered an issue while working with this chip. To trigger an over-voltage event, I continuously inject a 7V voltage into the VEXT pin. The software successfully detects the VEXTO event in the Supply Event Status Register.

However, after I clear the event by writing a 1 to the register, I can no longer detect the VEXTO event again. The event only appears again if I stop the fault injection and re-inject it. Why is this happening?

I was hoping to implement a debounce mechanism by continuously polling the VEXTO bit, but this approach doesn't seem to be feasible.Can you help me?

UJA1169TK 

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JozefKozon
NXP TechSupport
NXP TechSupport

Dear Baikian,

please note, the UJA1169TK is End Of Life. The recommended replacement is UJA1169ATK. This is a normal behavior. If you clear the fault, it means the OV fault is not present anymore and you need to start the fault injection again. 

With Best Regards,

Jozef

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Baikian
Contributor II

I haven't tested the other registers yet, such as the System Event Status Register. Do they follow the same mechanism?

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