This application note describes the changes of the Window Builder code generator that have been released in the latest PEG revision (2.3.13). To fix a bug in the code generator it had become necessary to introduce some changes. The attached document describe the changes in more detail and explain how to deal with them to avoid messing up user code interleaved in the generated code.

Q: How should I start to evaluate PEG? A:   Download: Desktop and Hardware Demos       Request for Window Builder  -  The free download is the full version of Window Builder, but no source code is provided, so applications can only be developed on provided compiled libraries (this by default is Windows, but can be extended to a EVB such as the Tower System).        Request for further evaluation please contact Freescale sales or distributor representative. Q: Is PEG software supported on NON-Freescale and Freescale silicon? A: Yes, PEG Software can be licensed for for NON-Freescale and Freescale silicon. There is a discount when used with Freescale silicon. Q:  Is the cost limited to 10,000 pieces? A:  There are 4 licensing models.       1) PEG Base Single Product/MCU (3 seats, <=10,000 units, 1 year support) is specific to the processor used AND the specific name and model of the customer end product.      2) Upgrade - Unlimited Run-time for PEG Base:  There are NO limits on the number of run-time units for the PEG Base Single Product/MCU      3) Upgrade - Same MCU across  Product Family (+3 seats, unlimited run-time): Supports a family of customer end products that use the same processor      4) Upgrade - Multi MCU across  Product Family (+6 seats, unlimited run-time): Supports a family of customer end products that use multiple processors Q: Is technical support included? A:  One year of support is included with the purchase of a license and can always renew. Q: How does the actual GUI image (in the frame buffer) get updated through interrupt routines or some other method. A:  PEG implemented a scheduler that runs at a defined rate (20 times per second by default) and quickly checks a messaging queue.  If updates to the image are required, then the appropriate actions are taken to update the screen. Q: How is the frame buffer decided on?  Does PEG do it as needed or does the designer set the size and update as needed? A: PEG will define the require space for the frame buffer depending on the screen resolution, color depth, and number of buffers (i.e double-buffering, multiple surfaces, etc…) Q: Do we have examples of wave form generation code with anti-aliasing filters? A: There are examples of PEG drawing a variety of graphs (in the demo folder of PEG). Q: What drivers hardware and screen drivers are supported? A: PEG screen drivers can be developed for virtually any processor/controller. The list here includes devices for which drivers currently exist. Q: How can I purchase PEG? A: You can purchase it direct please contact [email protected] or from a number of distributors/re-sellers:      - AIC Japan      - eCOS      - eSOL      - Express Logic      - Green Hills Software      - Microdigital      - Quadros      - Arrow      - Future      - Advent     

How can I distinguish between various MSC8154/MSC8156 devices? You can read the System Part and Revision ID Register (SPRIDR) from address  to get the part ID and revision ID numbers. Device             SPRIDR[PARTID] MSC8154                0x8304 MSC8154EC           0x831C MSC8154E             0x830C MSC8156               0x8302 MSC8156EC           0x831A MSC8156E             0x830A Revision           SPRIDR[REVID] Rev. 1                       0x0000 Rev. 2                       0x0001 [ return to top ] My configuration sets up the L2 unified cache/M2 memory to 256KB of M2 and 256 KB of L2 cache.  Does this mean L2 cache is 8 ways of 32 KB each? No. The L2/M2 is 512 KB, arranged in 8 ways of 64 KB each way. In your configuration, the L2 cache becomes 4 ways. Each way is still 64 KB. [ return to top ] Does an M3 ECC event trigger an interrupt? M3 memory is ECC-protected so a single-bit error is detected and corrected, therefore an interrupt is not necessary. [ return to top ] The L2 cache features 4 L2 software prefetch channels.  Are there 4 software prefetch channels per core or is this the total number per device? The L2 cache is private for each core, therefore the 4 software prefetch channels are per core. Each core configures its own set of L2 software prefetch registers. Each core can only configure its own L2. The L2 software prefetch registers cannot be configured externally from the DSP subsystem. [ return to top ] Do I need an I2C serial EEPROM for loading of the Reset Configuration Word (RCW)? No, there are other options for loading of the RCW besides the I2C serial EEPROM. Multiplexed RCW loading option(RCW_SRC[0:2]=000) - all 64-bits of the RCW are loaded in four passes using the external pins RC[15:0]  using the /RCW_LSEL[0:3] pins as lane select signals. Reduced RCW loading option (RCW_SRC[0:2]=011) - some bits of the RCW are latched from external pins and some bits are loaded from default hard-coded values. [ return to top ] How does MSC8156 MAPLE-B TVPE support Viterbi and Turbo decoding? Turbo and Viterbi decoding are supported by MSC8156 MAPLE-B TVPE in same µcode. You can initialize the Maple with one TVPE standard, plus some Viterbi parameters. Then you can use different Buffer Descriptors for Turbo and Viterbi. Note that MAPLE-B doesn't support multiple Turbo standards with the same µcode because Maple µcode is standard specific and a µcode re-load is required to switch from one standard to another. So supporting a mixture of users of different standard in real time cannot be done with current MAPLE-B.  Turbo and Viterbi decoding are supported in same µcode, since Viterbi decoding parameters are fully configurable and are not standard related. [ return to top ] I want to use the Debug and Profiling Unit (DPU) in the MSC8156 to log information into the virtual trace buffer. I have set up the DPU registers for core 0. How do I set up the DPU for the other cores 1/2/3/4/5 since there is only one set of DPU registers? Each DSP subsystem includes a DPU. Each core can access its own DPU registers using the same physical addresses. [ return to top ] I only need to reset an individual core in the MSC8156. How can I do that? All cores are reset together. There is not a method to reset a particular core in the MSC8156. [ return to top ] The MSC8156 Reference Manual shows the default DDR1 and DDR2 memory address spaces are 512 MB. How do I change the memory space to 1 GB? The MSC8156 Reference Manual shows the DDR address spaces as follows: 0x40000000–0x5FFFFFFF      DDR1 Memory (default value)                                               512 M 0x60000000–0x7FFFFFFF      Reserved.  Used for DDR1 memory if configured for 1 GB.      512 M 0x80000000–0x9FFFFFFF      DDR2 Memory (default value)                                               512 M 0xA0000000–0xBFFFFFFF     Reserved. Used for DDR2 memory if configured for 1 GB.       512 M After reset, the default DDR1 and DDR2 memory space is 512 MB. To increase to 1GB DDR memory range, you need to configure the CLASS registers as follows: For DDR1 memory controller, change C0EAD5 from the reset value of 0x0005FFFF to 0x0007FFFF [ return to top ] What is the maximum heat sink attachment force to avoid damaging the solder balls? Detailed information about the Flip-Chip Plastic Ball Grid Array (FC-PBGA) package type devices (MSC8144 and MSC8156) can be found in this document FC-PBGAPRES.pdf The maximum heat sink attachment force is 4 Newtons (10 lb force). [ return to top ] What does the NO_INC bit indicate in the DMA buffer descriptor BD_ATTR field? When would you use this? You can set NO_INC if you want to transfer to or from the same address. The address will not be incremented. For example, if you want to fill memory with data from a single memory location, you will need to set NO_INC for the source. However, the destination will have the NO_INC bit cleared. [ return to top ] If a MSC8156 DMA port A or B bus error happens, i.e., DMAERR[PAE] or DMAERR[PBE] bit is set, can I clear these bits and continue with the DMA operation? A port error will freeze the DMA channel so clearing the error bit has no effect. In this case, the DMA channel needs to be reinitialized before it can be used again. [ return to top ] If a DMA BD size 0 error occurs, i.e., DMAERR[BDSZ] is set, to indicate that the buffer descriptor field BD_SIZE is cleared, how can I tell which DMA channel is associated with the error? The DMAERR register does not indicate which channel accessed the BD with size 0. However, you can check the DMACHCRx registers to determine which channel did not finish the transfer by checking if the active ACT bit is high. A channel that does not encounter the error will finish (ACT bit gets cleared). [ return to top ] .

See a demonstration of PEG Software to develop graphical user interfaces (GUI) for consumer, industrial and automotive display applications.

See an overview of PEG software for developing graphical user interfaces (GUI) for consumer, industrial and automotive display applications.

The following wikis provide useful “how to” and FAQ information not available on Freescale websites or forums. The links below provide useful design resources for product designers and users. eGUI PEG GUI StarCore DSPs

The PEG GUI wiki provides useful “how to” and FAQ information not available on Freescale websites or forums. The links listed below provide useful design resources for product designers and users. PEG GUI discussions under Freescale Other Solutions in the Freescale Community (all spaces) PEG GUI videos PEG GUI FAQ Website