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KW45 Understanding applications code size Hello, I would like to know my application code size. On MCUXpresso the output console shows 174012 which is 170 bytes. But i dont know if this includes the BLE stack ? kw45b41_nbu_ble_1_9_12_3.sb3 ? if yes how to know each part size. Any guide please ?  Kind Regards, MSM. Re: KW45 Understanding applications code size Thank you for the reply. Regards. MSM. Re: KW45 Understanding applications code size Hello MSM, Hope you are doing well. The application code size is the one that the IDE shows. Something important to remark is that the nbu.sb3 is load on the NBU core. I would recommend checking the Getting Started with the KW45B41Z Evaluation Kit | NXP Semiconductors Regards, Ricardo
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UART- S32K144 EVB I am currently working with the S32K144-EVB and attempting to perform data transmission and reception using UART. However, I am encountering difficulties with the UART configuration, especially since I am new to S32Design Studio. Initially, I tried the example UART project and successfully received the transmitted value. However, when I created a new project and configured the UART, I did not receive any data. Could you please provide guidance on how to properly configure UART in a new project. Re: UART- S32K144 EVB Hi @DIVYAJ1, Sorry for the misunderstanding, but are you using config tools or are you configuring the drivers yourself with registers? Following the thread, I was giving recommendations on how to configure the UART by using the GUI for the drivers, but the project you shared does not use these generated configurations. If you need to configure the example in bare metal, please follow AN5413: S32K1xx Series Cookbook, which includes an example for a simple UART 9600 baud transfer to a COM port on a PC in chapter 2.7. Best regards, Julián Re: UART- S32K144 EVB Here is the project file; Re: UART- S32K144 EVB Hi @DIVYAJ1, Could you share your code (main.c)? Maybe you are missing some steps initializing or using the functions. The basic uart project should look something like this: int main(void) { /* Initialize and configure clocks * - see clock manager component for details */ CLOCK_SYS_Init(g_clockManConfigsArr, CLOCK_MANAGER_CONFIG_CNT, g_clockManCallbacksArr, CLOCK_MANAGER_CALLBACK_CNT); CLOCK_SYS_UpdateConfiguration(0U, CLOCK_MANAGER_POLICY_AGREEMENT); /* Initialize pins * - See PinSettings component for more info */ PINS_DRV_Init(NUM_OF_CONFIGURED_PINS0, g_pin_mux_InitConfigArr0); /* Initialize for UART_PAL */ UART_Init(&uart_instance, UART_PAL_CONFIG); /* Send a welcome message */ UART_SendDataBlocking(&uart_instance, (uint8_t *)welcomeMsg, strlen(welcomeMsg), TIMEOUT); } Best regards, Julián Re: UART- S32K144 EVB Hi, Thankyou for replying. I imported the file you provided and successfully received transmitted data in the debug terminal. However, after following the UART configuration steps to create a new project, I am only seeing ‘NULL’ in the debug terminal instead of the expected transmitted data. Re: UART- S32K144 EVB Hi @DIVYAJ1, In order to use UART, you can simply add the UART component and configure the pins through Config Tools:         If you want to use interrupts or a callback for your reception and transmission, then the IntCtrl driver must also be added, but for a simple uart configuration that should be enough. I've attached a simple example which echoes the inputs through a serial terminal through UART1 (connected to the EVB's USB): Best regards, Julián
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MC33774Aドライバードキュメント MC33774AドライバーコードでのInitMap()関数とハッシュテーブルの作成を理解できません。これらの概念を理解するのに役立つドキュメントはありますか? よろしくお願いします。 モハナG V
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imxrt1176 freertos linkerscript file problem I am trying to debug my project with freertos. However, I could not debug it. After some digging, I found that project.ld (linker file) does not include the below line. (blue marked line). This below SS belongs to app which can be debug. However, in my project, linker script file is as below; There must be a line between marked two lines in blue. Since this linker script file is located in  "Debug folder", it is deleted when I add the required command manually. Therefore I need that  code line. How can I add it in order for linkerscript add automatically? Re: imxrt1176 freertos linkerscript file problem @diego_charles  thank you very much Re: imxrt1176 freertos linkerscript file problem Hi @burhanhagi  To avoid your linker script modifications getting overwriten you can un-tick the Manage linker script  But this may not be the best solution since MCUXpresso will not longer update the linker script.  This section should be included to new project  when the FreeRTOS OS is selected. See the below snapshot.  Now, if you do not want to create a new project, you can use the Manage SDK options and select FreeRTOS. After clicking OK the below window will pop-up. Please consider that the IDE will ask if you wish to update your current SDK drivers, depending on your project and its configuration this could, in the worst scenario some clonficts, just be aware of that.  After buiding, you should see the missing section.  I really hope this could help you  Diego
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如果比较寄存器设置为 0,则 ENET PTP 比较输出永远不会触发——新的芯片勘误表? 您好!我一直在努力在我们的系统中实现 PTP 比较(又名时间脉冲)。目标是从设备中生成每秒一次的时间脉冲,以便我们可以将其时钟同步与 PTP 系统中的其他设备进行比较。 在执行此操作时,我遇到了一个相当奇怪的问题:如果将值 0 写入 PTP 计时器比较寄存器,则不会生成任何比较事件。(1、ENET->ATPER) 中的任何其他值都可以正常工作并生成事件,但 0 不行。据我所知,这似乎是一个以前未知的芯片勘误表,因为数据表中没有提到 0 对于该寄存器来说是非法的,事实上,在这里使用 0 来在秒的顶部生成脉冲是很常见的。 我从我们的代码库中提炼出了一个产生该问题的小例子: /* * Timepulse triggering bug demo */ #include #include #include #include // PTP clock is ticked at 25MHz, 1/25MHz = 40ns increment const uint8_t timeIncrement = 40; // Set HW nanosecond counter to roll over ever 4 seconds. // The max value here is about 4.2 seconds, so this is as high as we can have it // while still keeping it an integer number of seconds const uint32_t nanosecondCounterRolloverVal = 4000000000; const uint32_t ONE_SECOND_NS = 1000000000; void enableENETClock() { /* Init Enet PLL. */ const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = { .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */ .enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */ .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */ .src=0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ .enableClkOutput1 = true, /* Enable the PLL providing the ENET2 125MHz reference clock */ .loopDivider1 = 1, /* Set frequency of ethernet reference clock to 50 MHz */ }; CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); /* Set ENET Ref clock source. */ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; /* Set ENET2 Ref clock source. */ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; } void initENET() { CLOCK_EnableClock(kCLOCK_Enet); ENET_Reset(ENET); } void initPTPClock() { // Software reset timestamp module ENET->ATCR = ENET_ATCR_RESTART_MASK; while(ENET->ATCR & ENET_ATCR_RESTART_MASK) {} // Configure increment. ENET->ATINC = ENET_ATINC_INC(timeIncrement); // Reset fine counter at the defined period ENET->ATPER = nanosecondCounterRolloverVal; // Start counter counting. ENET->ATCR |= ENET_ATCR_EN_MASK; } void setCurrentTime(uint32_t timeCounts) { ENET->ATVR = timeCounts; } uint32_t readCurrentTime() { // Note: This is based on ENET_Ptp1588GetTimerNoIrqDisable. // (...because the datasheet doesn't actually really explain how to read the timer) // Issue a capture command and wait for it to complete. // A comment in FSL HAL says this takes about 6 timestamp clocks, meaning about 240ns. ENET->ATCR = ENET_ATCR_CAPTURE_MASK; while(ENET->ATCR & ENET_ATCR_CAPTURE_MASK) {} return ENET->ATVR; } int main() { enableENETClock(); initENET(); initPTPClock(); uint64_t nextTimepulseTime = ONE_SECOND_NS; const uint32_t timepulsePeriod = ONE_SECOND_NS; setCurrentTime(0); // Initialize the timepulse and set it to go off at the initial time ENET_Ptp1588SetChannelCmpValue(ENET, kENET_PtpTimerChannel1, nextTimepulseTime % nanosecondCounterRolloverVal); printf("First timepulse will fire at %" PRIu64 "\n", nextTimepulseTime % nanosecondCounterRolloverVal); nextTimepulseTime += timepulsePeriod; ENET_Ptp1588SetChannelOutputPulseWidth(ENET, kENET_PtpTimerChannel1, false, 31, false); // Wait for timer mode change to go through, otherwise we might write TCCR too early // and it will replace the first compare value with the second one // This is not documented in the datasheet but it doesn't work without it... while((ENET->CHANNEL[kENET_PtpTimerChannel1].TCSR & ENET_TCSR_TMODE_MASK) == 0) {} // Feed in the next time as well ENET_Ptp1588SetChannelCmpValue(ENET, kENET_PtpTimerChannel1, nextTimepulseTime % nanosecondCounterRolloverVal); printf("Second timepulse will fire at %" PRIu64 "\n", nextTimepulseTime % nanosecondCounterRolloverVal); nextTimepulseTime += timepulsePeriod; // Loop, printing when each timepulse happens while(true) { // Did the timepulse fire? if(ENET_Ptp1588GetChannelStatus(ENET, kENET_PtpTimerChannel1)) { const uint32_t nextTimepulseCounts = nextTimepulseTime % nanosecondCounterRolloverVal; printf("Timepulse fired, current PTP counter register = %010" PRIu32 ". " "Configuring timepulse after the next to fire at %010" PRIu32 "\n", readCurrentTime(), nextTimepulseCounts); // Write the next target time to the register ENET_Ptp1588SetChannelCmpValue(ENET, kENET_PtpTimerChannel1, nextTimepulseCounts); nextTimepulseTime += timepulsePeriod; // Finally clear the timer flag. This has to be done after loading in the next trigger time // as it triggers a load of the TCCR register into the comparator. ENET_Ptp1588ClearChannelStatus(ENET, kENET_PtpTimerChannel1);; } } } 执行后,会打印: ============== Power On ============== First timepulse will fire at 1000000000 Second timepulse will fire at 2000000000 Timepulse fired, current PTP counter register = 1000008160. Configuring timepulse after the next to fire at 3000000000 Timepulse fired, current PTP counter register = 2000000440. Configuring timepulse after the next to fire at 0000000000 Timepulse fired, current PTP counter register = 3000000440. Configuring timepulse after the next to fire at 1000000000 正如您所见,代码在 0 秒的时间脉冲应该触发的位置冻结。 但是,如果我将行“uint64_t nextTimepulseTime = ONE_SECOND_NS;”更改为“uint64_t nextTimepulseTime = ONE_SECOND_NS + 1;”(确保 0 永远不会写入 TCCR),一切都会正常运行。现在打印: ============== Power On ============== First timepulse will fire at 1000000001 Second timepulse will fire at 2000000001 Timepulse fired, current PTP counter register = 1000009000. Configuring timepulse after the next to fire at 3000000001 Timepulse fired, current PTP counter register = 2000000480. Configuring timepulse after the next to fire at 0000000001 Timepulse fired, current PTP counter register = 3000000440. Configuring timepulse after the next to fire at 1000000001 Timepulse fired, current PTP counter register = 0000000480. Configuring timepulse after the next to fire at 2000000001 Timepulse fired, current PTP counter register = 1000000480. Configuring timepulse after the next to fire at 3000000001 Timepulse fired, current PTP counter register = 2000000480. Configuring timepulse after the next to fire at 0000000001 Timepulse fired, current PTP counter register = 3000000440. Configuring timepulse after the next to fire at 1000000001 Timepulse fired, current PTP counter register = 0000000480. Configuring timepulse after the next to fire at 2000000001 Timepulse fired, current PTP counter register = 1000000480. Configuring timepulse after the next to fire at 3000000001 Timepulse fired, current PTP counter register = 2000000480. Configuring timepulse after the next to fire at 0000000001 Timepulse fired, current PTP counter register = 3000000480. Configuring timepulse after the next to fire at 1000000001 Timepulse fired, current PTP counter register = 0000000440. Configuring timepulse after the next to fire at 2000000001 Timepulse fired, current PTP counter register = 1000000440. Configuring timepulse after the next to fire at 3000000001 Timepulse fired, current PTP counter register = 2000000480. Configuring timepulse after the next to fire at 0000000001 Timepulse fired, current PTP counter register = 3000000480. Configuring timepulse after the next to fire at 1000000001 Timepulse fired, current PTP counter register = 0000000480. Configuring timepulse after the next to fire at 2000000001 Timepulse fired, current PTP counter register = 1000000480. Configuring timepulse after the next to fire at 3000000001 Timepulse fired, current PTP counter register = 2000000480. Configuring timepulse after the next to fire at 0000000001 Timepulse fired, current PTP counter register = 3000000480. Configuring timepulse after the next to fire at 1000000001 Timepulse fired, current PTP counter register = 0000000480. Configuring timepulse after the next to fire at 2000000001 据我所知,该代码应该可以在原始版本中运行,而事实上它却不能运行,这是一个勘误表。如果 NXP 的某个人能告诉我这是否有意义,我将非常感激。这不是什么大问题,但它确实应该出现在勘误表中,以避免未来的人们再次调试同样的问题。 i.MXRT 105x i.MXRT 106x 回复:如果比较寄存器设置为 0,ENET PTP 比较输出将永远不会触发——新的芯片勘误表? 嗨,感谢您的浏览!这是在 MIMXRT1062 上。 Re: ENET PTP Compare output never fires if compare register is set to 0 -- new chip errata? 嗨,Kan! 很抱歉挖坟,但我终于抽出时间在硬件上尝试了一下。我首先尝试了解决方法 1(在 ATCR 中设置 PINPER 和 PEREN 位)。这种方法似乎行不通——当 TCCR 设置为 0 时,计时器仍然不会触发,行为没有任何改变。解决方法 2(防止 TCCR 小于 ATINC)似乎可以正常工作。不过,在我的测试中,将 TCCR 设置为小于 ATINC 但大于 0 的值(例如 1)确实有效,因此这种变通方法的范围可能有点太广了。但是,这对我的申请来说不是问题。 此外,在测试过程中,我还发现了另一个问题。将 TCCR 设置为小于 ATINC 的值(低于 ATPER)也会导致定时器永远不会触发。根据这里的设置,该值将大于 3999999960 且小于 4000000000。这似乎是对现有勘误表的延伸。 我还测试了该错误是否受到校正增量 (INC_CORR) 的影响,方法是将 ATINC.INC_CORR 设置为 42,将 ATCOR 设置为 1(这样每隔一个 PTP 时钟周期就会使用校正)。使用这些设置后,我在使用 INC_CORR 范围内的时间戳时没有遇到问题,例如3999999960。这似乎表明 INC_CORR 不会影响此勘误的范围。(而且这是件好事,我可不想遇到那种因为恰好在校正增量上运行,导致我的时间脉冲在数千次执行中随机失败一次的罕见错误!)
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i.MX 6はLPDDR2-1066チャネルをサポートしていますか? MCIMX6Q6AVT10ADを使用しています。 これまで、LPDDR2メモリインターフェースの周波数について質問を受けました。   IMX6DQRM.pdfによると、『i.MX 6Dual/6Quad Applications Processor Reference Manual』(改訂版)6、05/2020)、第1.4章特徴」、SoCは1/2LPDDR2-1066チャネルをサポートします。   しかし、別の文書によると、IMX6DQAEC.pdf、「i.MX 6Dual/6Quad オートモーティブ&インフォテインメント...」、データシート(Rev.6、11/2018)、第1.2章特徴」、1/2 LPDDR2-800チャンネルのみをサポートします。   明確にしていただけますか? i.MX6 全て i.MX6Quad
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iMX93 Windows 11 IoT bluescreens when connecting USB device The Windows 11 IoT version from the "i.MX Windows 10/11 IoT Enterprise Quick Start Guide​" has working USB but is outdated. I am trying to use a newer version of Windows 11 IoT Enterprise LTSC 2024. Using the the Steps outlined in the Quick Start Guide, I - first downloaded Windows W21H2-1-5-1 BSP prebuilt binaries - then downloaded the newest Win 11 IoT LTSC 2024 arm64 .iso and extracted its install.wim - after that I built an image using make-winpe-enterprise.cmd - applied it to an sd-card and installed windows to a board Now the moment I plug any USB device into one of the USB-Host ports windows bluescreens. I am using the same board and uboot+uefi as with the older (working) version. Analyzing the bluesceen dump shows that Windows crashes usbehci!InterlockedOr 0c ffff888a`9c04f630 fffff800`45c3b0cc nt!KeBugCheck2+0xaf0 0d ffff888a`9c04fc10 fffff800`45d1193c nt!HalBugCheckSystem+0x8c 0e ffff888a`9c04fc50 fffff800`45d11d40 nt!WheaRecoveryBugCheck+0x6c 0f ffff888a`9c04fc70 fffff800`470a185c nt!WheaReportHwError+0x3f0 10 ffff888a`9c04fd30 fffff800`45d156a4 RADARM!RadArmSeaCallback+0x2bc 11 ffff888a`9c04fee0 fffff800`45c4108c nt!WheaSignalHandlerOverride+0x34 12 ffff888a`9c04fef0 fffff800`45a5f440 nt!HalWheaHandleSea+0x4c 13 ffff888a`9c04ff80 fffff800`45a5f534 nt!KiAbortException+0x280 14 ffff888a`9c04ffc0 fffff800`45993c00 nt!KiSynchronousException+0x94 15 ffff888a`9c0500b0 fffff800`4599285c nt!KzSynchronousException+0x24 16 ffff888a`9c050110 fffff800`442b10dc nt!KiArm64ExceptionVectors+0x5c 17 ffff888a`9c050480 fffff800`442bcaa4 usbehci!InterlockedOr+0xc 18 ffff888a`9c050480 fffff800`442b6d48 usbehci!EHCI_AllocTd+0x84 19 ffff888a`9c0504b0 fffff800`442be784 usbehci!EHCI_OpenBulkOrControlEndpoint+0x148 1a ffff888a`9c050520 fffff800`442d3164 usbehci!EHCI_OpenEndpoint+0x134 1b ffff888a`9c050590 fffff800`44302e04 USBPORT!MPx_OpenEndpoint+0xd4 1c ffff888a`9c0505d0 fffff800`44301af8 USBPORT!USBPORT_OpenEndpoint+0x994 1d ffff888a`9c050650 fffff800`442dede0 USBPORT!USBPORT_NeoCreateDevice+0x300 1e ffff888a`9c0506d0 fffff800`494f7f00 USBPORT!USBPORTBUSIF_CreateUsbDeviceV7+0xa0 1f ffff888a`9c050750 fffff800`49519e18 usbhub!UsbhCreateDevice+0x278 20 ffff888a`9c050830 fffff800`49518278 usbhub!UsbhReset1Complete+0x118 21 ffff888a`9c0508a0 fffff800`494ef838 usbhub!UsbhEnumerate1+0x218 22 ffff888a`9c0508f0 fffff800`494effe8 usbhub!UsbhHubDispatchPortEvent+0x6f0 23 ffff888a`9c050960 fffff800`494f61b4 usbhub!UsbhHubRunPortChangeQueue+0x288 24 ffff888a`9c050a10 fffff800`494eeb54 usbhub!Usbh_PCE_wRun_Action+0x194 25 ffff888a`9c050a50 fffff800`494f1ce4 usbhub!UsbhDispatch_PortChangeQueueEventEx+0x12c 26 ffff888a`9c050aa0 fffff800`494efa88 usbhub!UsbhPCE_wRun+0x8c 27 ffff888a`9c050ad0 fffff800`459f2618 usbhub!UsbhHubProcessChangeWorker+0x148 28 ffff888a`9c050b20 fffff800`45b27818 nt!IopProcessWorkItem+0x98 29 ffff888a`9c050b80 fffff800`45a9ca80 nt!ExpWorkerThread+0x148 2a ffff888a`9c050d50 fffff800`4599be4c nt!PspSystemThreadStartup+0x50 2b ffff888a`9c050d90 00000000`00000000 nt!KiStartSystemThread+0x24 more specifically on this "ldsetal" instruction: usbehci!InterlockedOr: fffff800`442b10d0 900000f0 adrp xip0, usbehci!__security_cookie (fffff800442c4000) fffff800`442b10d4 101240b9 ldr wip0, [xip0, usbehci!_AtomicsV81Support (x16+10h)] fffff800`442b10d8 70000036 tbz wip0, #0, usbehci!_InterlockedOr+0x14 (fffff800442b10e4) fffff800`442b10dc 0030e1b8 ldsetal w1, w0, [x0]  I verified that usbehci_fix.inf from BSP is installed and the registry key "NoInterlockedOpOnCommonBuffers" is present. How can I fix this crash? Re: iMX93 Windows 11 IoT bluescreens when connecting USB device Thank you for your reply. I used the install.wim from en-us_windows_11_iot_enterprise_ltsc_2024_x64_dvd_f6b14814.iso I am unable to reproduce the issue now. I think the Issue was caused by a defective sd-card. In theory it could also be caused by make-winpe-enterprise.cmd /apply failing to copy install.swm  correctly. I used FastCopy to verify the files on the sd-card were identical to those in out\winpe-imx-sdcard-layout and noticed the corrupted install.swm. Since then I started to verify the files are copied correctly and haven't had any more problems. I am marking this as resolved. Re: iMX93 Windows 11 IoT bluescreens when connecting USB device Can you share the exact name of the ISO?
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DAC0 DMA on iMXRT1170 Dear Forum, We're trying to implement DAC0 DMA procedure with iMXRT1170-EVK. Reference manual states that DMA is supported but peripheral tool does not have such options:   We've noticed there's no example project in SDK with DAC0, so we tried to port it from K20 family. The functional diagram is very similar, however register maps differs. Can someone provide an example or reference implementation of DAC0 working with DMA on iMXRT1170? Re: DAC0 DMA on iMXRT1170 Ok, I'll try to follow this tutorial: https://community.nxp.com/t5/MCUXpresso-Config-Tools/eDMA-component-abilities-shown-on-ADC-measurement-example/ta-p/1415444 Re: DAC0 DMA on iMXRT1170 I would like to give you more but there are only the SDK examples for DMA and DAC separately as reference for the RT1170. Re: DAC0 DMA on iMXRT1170 Ok, thanks. Do you have any tips on porting code from other board or example? Re: DAC0 DMA on iMXRT1170 Hi, Thank you so much for your interest in our products and for using our community. DMA is supported in Buffered mode: Regarding the comparison of the RT1170 DAC with the Kinetis DAC, at high level approach both modules seem similar, but the peripherals are not exactly the same. And sorry for the inconvenience but there is no DAC-DMA example available for RTs. Have a nice day!
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S32G boards Hello, Q1: I noticed that we have S32G-VNP-EVB and S32G-VNP-EVB3, assuming that they are similar and there are only some modifications in EVB3, right? Q2: As we know that S32G-VNP-EVB includes platform board and processor board So does that mean there are  platform board and processor board for EVB and platform board - 3 and processor board - 3 for EVB3? Q4: I can find the schematic of processor boards SCH-32170_B4.pdf and S32G-PROCEVB3-S board – REV A Schematics.pdf they should be belong to EVB and EVB3, right? Q5: assuming that EVB3 processor board is based on EVB processor board why in the Revision History of S32G-PROCEVB3-S board – REV A Schematics.pdf it cannot find the history of SCH-32170_B4.pdf? Q6: for platform board, I can only find SCH-30081_D.pdf is it belong to EVB? where to find another version for EVB3? Thanks Re: S32G boards It is clear now, thank you, Daniel Re: S32G boards Hi, Below will be some comments on regards of your questions: Q1: I noticed that we have S32G-VNP-EVB and S32G-VNP-EVB3, assuming that they are similar and there are only some modifications in EVB3, right? [DA]: Don't know if we can say they are similar. They do have differences that could impact your development (i.e. there are 2 UART ports available under EVB3, while there is only 1 under EVB). We say that they are similar on regards of they both were designed for S32G platforms. Q2: As we know that S32G-VNP-EVB includes platform board and processor board. So does that mean there are platform board and processor board for EVB and platform board - 3 and processor board - 3 for EVB3? [DA]: We understand that the processor board is the one that relates to the EVB/EVB3 product. The platform board relates to the PLATEVB product. There is no specific PLATEVB3 product, only PLATEVB with different revisions. Q4: I can find the schematic of processor boards SCH-32170_B4.pdf and S32G-PROCEVB3-S board – REV A Schematics.pdf they should be belong to EVB and EVB3, right? [DA]: We understand that you are saying the following: EVB -> SCH-32170_B4.pdf EVB3 -> S32G-PROCEVB3-S board – REV A Schematics.pdf If so, this is correct. Q5: assuming that EVB3 processor board is based on EVB processor board why in the Revision History of S32G-PROCEVB3-S board – REV A Schematics.pdf. it cannot find the history of SCH-32170_B4.pdf? [DA]: It can be based, but the design is different. As of why it was not a revision for EVB, this decision seems to be related to the design team itself. It is not common to add a revision for a different board even if it shares similarities. Q6: for platform board, I can only find SCH-30081_D.pdf is it belong to EVB? where to find another version for EVB3? [DA]: PLATEVB does not relates to EVB or EVB3, it is a different product. For that situation, PLATEVB seems to be shared with both EVB and EVB3. Please, let us know.
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eDMA ping-pong buffer sorting Good day to all! I use IMX8ULPIEC processor and i programming SAI interface under m-33 core. I receive data in the format ABC_ABC_ABC_ABC... via eDma using the SAI_TransferReceiveLoopEDMA() function and thus receive a ping-pong buffer for two arrays storing ABCABCABC alternately. However, I would like the data after reception to look like this: AAAA......BBBB......CCCC...(end) and also issued alternately in two buffers as in the ping-pong buffer. Is it possible to do this within one eDMA stream without stopping reception? Are there any examples of similar packaging? Thanks in advance. i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX8ULP Re: eDMA ping-pong buffer sorting I figured out the problem. I had to change the function SAI_TransferReceiveLoopEDMA() a little, called it SAI_TransferReceiveLoopEDMASetuped(). If someone encounters a similar problem, I am attaching a file with the source code of the modified function and its application.
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S32K146 issue where BusFault is triggered during DFLASH initialization 1.According to the customer's software engineer, after the initialization triggers the BusFault, the error of the corresponding address will be repaired according to the logic of the software (the erasure operation will be performed), but during the erasure process, it is found that the FTEx FSTAT MGSTATO MASK is set to 1, resulting in the erasure operation cannot be successfully executed.Under what circumstances will FTEx FSTAT MGSTATO MASK be set to 1? 2.Why does the SEGGER J_Fflash software report a message "Erase Failed" when I use SEGGER J_Fflash software and JLink debugger to erase, but I can find that the erase has been implemented on KEIL? 3.Why can't the executed erase function in the software be successfully erased, but the external debugger can? Re: S32K146 issue where BusFault is triggered during DFLASH initialization Hi @Louis1916, It is hard to say, the tool uses the same FTFC command to erase the sector, but the MCU is likely in the default (out of reset) configuration during the flash operation while the core and other masters are inactive. Re: S32K146 issue where BusFault is triggered during DFLASH initialization Hi Daniel. What the customer engineer was puzzled about: The chip that uses SEGGER J_Fflash software and JLink debugger to erase the single SECTOR (0x10004800--0x10004FFF) with BusFault can operate normally. However, the underlying function of the software to perform the erase operation is FLASH_DRV_CommandSequence(), and an error is reported。Why can it be erased normally by the tool, but it can't be directly commanded?Thanks! Re: S32K146 issue where BusFault is triggered during DFLASH initialization Hi @Louis1916, The flash got probably damaged, because this is just one sector on one MCU sample, there is nothing we can do, unfortunately. Hard to determin the root cause, it could be due to ESD, for example. Refer to AN12130 Production Flash Programming Best Practices for S32K1xx MCUs 5 Common problems https://www.nxp.com/docs/en/application-note/AN12130.pdf Re: S32K146 issue where BusFault is triggered during DFLASH initialization Hi Daniel. 1.The verification fails when erasing,Under what circumstances does the sector erase verification fail and what are the reasons? The corresponding sector address is (0x10004800--0x10004FFF), it is triggered repeatedly The BusFault is incorrect and belongs to a precise data access conflict, and repeated attempts are made to clear the data of the entire SECTOR.This error condition only occurs in one SECTOR. Except for the chip that has already had the error condition "BusFault triggered and is a precise data access violation", the other chips failed to reproduce the error; The customer can ensure that the erase and write times of the DFLASH part of the chip are within its cycle life; 2.The system clock configuration is determined to be within the specification;   The underlying function of the software to perform the erase operation is FLASH_DRV_CommandSequence(), and the specific code of the function is shown in the following figure: Re: S32K146 issue where BusFault is triggered during DFLASH initialization Hi @Louis1916, 1. MGSTAT0 is set when the Sector Erase verification fails, that mean the sector is not properly erased. Have you tried repeating the Sector Erase operation at the sector? Do you see the problem with just one sector or more? Can you replicate it on other MCUs or is it just one sample that does that? Note that the cyclic endurance of the flash is 1000 cycles, above that, NXP does not gurantee its functionality. 2. Please contact KEIL 3. In Q2, you mentioned that SEGGER J_Flash software reports a message "Erase Failed" too. Is this a different scenario? What is the address of the sector? Is the system clock configuration within the specification? Regards, Daniel
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S32DS can't build freertos for S32K312 hi everyone When using 'SW32K3_FreeRTOS_10_5_1_UOS_3_1_0_DS_updatesite_D2304', generate routine for S32K312, compile fails.and where to download template software for S32K312EVK Re: S32DS can't build freertos for S32K312 Hi Select the "S32 Configuration Tool" menu then click on the desired configuration tool (Pins, Cocks, Peripherals etc...). Clicking on any one of those will generate all the components. Make the desired changes(if any) then click on the "S32 Configuration Tool->Update Code" button. Do you still encounter errors when you build after clicking Update Code? I refer to HOWTO: offline install S32K3 RTD 3.0.0 in S32DS v3.5 to install S32K3, and then install SW32K3_FreeRTOS_10_5_1_UOS_3_1_0_DS_updatesite_D2304.zip. No errors will be encountered when building. Sorry, I haven't seen the S32K312 examples since the version after S32K3 RTD 2.0.3. As you know, S32K3 has many derivatives, so to reduce effort, in the most recent RTD releases we only provide examples for K344, K358, and K396. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
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s32k3 hse advanced secure boot remove/update smr/cr entry Hi Nxp,     once a smr entry and cr entry installed,  1. how to update entry?  use the same api  ( service id)? is there a sample code available? 2. is it possible to remove this smr and cr entry? how to do it. thanks. Re: s32k3 hse advanced secure boot remove/update smr/cr entry There is a document NXP HSE BASIC FW FAQ.pdf within HSE Firmare installation. An answer you may find on page 10. I am not sure whether we have example code for this operation. I will further investigate.
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fs23 Lin mode swith question Hello, We encountered a question while debugging the FS LIN functionality. Specifically, we found that in debug mode, we cannot set the LINTRCV_FS23_TRCVMODE_OFF mode using the LinTrcv_fs23_SetMode() function. The code snippet is as follows: Std_ReturnType LinTrcv_fs23_SetMode(uint8 u8LinNetwork, LinTrcv_fs23_TrcvModeType eOpMode) { uint16 u16RegData = 0U; Std_ReturnType eStatus; LinTrcv_fs23_TrcvModeType eNewHwOpMode = LINTRCV_FS23_TRCVMODE_INVALID; /* Read M_LIN register. */ eStatus = Sbc_fs23_ReadRegister(SBC_FS23_M_LIN_ADDR, &u16RegData); if ((Std_ReturnType)E_OK == eStatus) { /* Set new register value. */ u16RegData &= ~(SBC_FS23_M_LIN_MODE_MASK | SBC_FS23_M_LIN_SLOPE_MASK| SBC_FS23_M_LIN_FS_DIS_MASK); if(TRUE == xG_drivers[u8LinNetwork].bLinSlowSlope) { u16RegData |= SBC_FS23_M_LIN_SLOPE_SLOW; } if(FALSE == xG_drivers[u8LinNetwork].bLinFailsafeDisable) { u16RegData |= SBC_FS23_M_LIN_FS_DIS_KEEP; } u16RegData |= ((uint16)eOpMode << SBC_FS23_M_LIN_MODE_SHIFT); eStatus = Sbc_fs23_WriteRegister(SBC_FS23_M_LIN_ADDR, u16RegData); .... /*Check the real hardware state*/ eStatus |= LinTrcv_fs23_GetMode(u8LinNetwork, &eNewHwOpMode); if((eNewHwOpMode == eOpMode) && ((Std_ReturnType)E_OK == eStatus)) { eStatus = (Std_ReturnType)E_OK; } else { eStatus = (Std_ReturnType)E_NOT_OK; } } return eStatus; } The eOpMode is LINTRCV_FS23_TRCVMODE_OFF,  the eNewHwOpMode  is LINTRCV_FS23_TRCVMODE_NORMAL. The manual states that in debug mode, LIN defaults to active mode. Is this behavior normal? Thanks! Re: fs23 Lin mode swith question Hi @gumu , I got confirmation from hardware team that it's a normal behaviour. In debug mode, the transceiver mode is forced ACTIVE. So even if you try and change the LIN_MODE field to OFFLINE (OFF, 2b00) then the transceiver stays in active mode. Re: fs23 Lin mode swith question Hi, I have to check with hardware team. Can you please let me know what version of FS23 that you have? Or what is the part number? Re: fs23 Lin mode swith question Hi Quang (@quangvuanh), Could you please help with this question from Anhui Zhitu Technology China? Thanks & BRs, Tomas
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より大きなシステムの一部としてのNNモデル - eIQ、Glowによるビルドプロセス こんにちは、eIQ + Glowなどのサードパーティベンダーの最適化により、複雑なシステムをAIモデルで強化することはどのように可能になるのか疑問に思います。私が理解した限りでは、これらは*推論*中にモデルとCPUの使用率を最適化するだけです。精度を達成するために必要な残りのモジュール、たとえば、データの前処理、特徴エンジニアリングは、グロービルドにこれらのステップを含める必要がある場合、手書きの方法でC言語で個別に記述する必要があります。では、これらの前処理ステップには最適化はありませんよね? さらに大局的に見ると、おそらくすでに独自のビルドプロセスを持っている複雑なシステムでは、Glow eccからHWへの最適化を活用できませんよね?「複雑な」システム全体に対して 1 つのビルド プロセスのみが存在する必要があります。
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How to connect the Not Connected Pin in LX2160? Dear NXP Support team, I have a question between LX2160 data sheet and reference schematic. In the LX2160 data sheet, "Not Connection" is guided to be left floating, but on page 18 of the reference circuit "LX2160-RDB-SCH", some pins are connected to the power rail with VDD. For inquiries, when designing a circuit, how should I connect the NC_P28/R27/U27/V28/W27/AA27/AC27/AD28/AE27/AF28/AG28 pins among the NC (Not Connection) pins? Connect to VDD or Left Floating? Refer to the below capture is from the reference schematic "LX2160-RDB-SCH", Thanks, Deega Jung Re: How to connect the Not Connected Pin in LX2160? Dear yipingwang, Thank you for your comment.  Thanks, Deega Re: How to connect the Not Connected Pin in LX2160? For LX2160A based design, successful operation is guaranteed when "NC pins" should be left floating. It should not be connected to VDD. Strictly follow the guidlines as mentioned in LX2 datasheet. Re: How to connect the Not Connected Pin in LX2160? Hi uipingwang, Thank you for your reply. I didn't know because I couldn't see the information about the LS2081A SOC. As a result of my review, the NC pins of NC_P28/R27/U27/V28/W27/AA27/AC27/AD28/AE27/AF28/AG28 are located in the area marked with a red-box in Layer-10 on the reference EV-kit PCB. It appears to have been connected to the bypass CAP (C434) of the VDD power rail of Layer-10 and to have connected the NC pins to the VDD to secure the current path. What is your opinion? Also, is there a way to check the datasheet of LS2081A? If you can, I would appreciate it if you could share. Thanks, Deega Re: How to connect the Not Connected Pin in LX2160? The LX2160ARDB was designed to support both LS2081A and LX2160A SOC's. The mentioned NC pins connected to VDD on RDB are required for LS2081A operation. For LX2160A, follow the guidelines given in LX2160A datasheet that is, NC pins should be left floating. Re: How to connect the Not Connected Pin in LX2160? Confirming with the AE team.
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s32k312 can't write dflash Hello! I want store some data into s32k312's DFlash. I can write data into address 0x10000000~0x1000FFFF successfully, but when I try to write data into 0x10010000, not worked. Below is my write code: write 0x1000E000write 0x1000E000 write 0x10010000 not workedwrite 0x10010000 not worked Is there some limit avoid me to write address after 0x10010000?  Re: s32k312 can't write dflash Hi @Vandarkholme, This should be the issue: Fixed in RTD 4.0.0 Regards, Daniel Re: s32k312 can't write dflash Hi! @danielmartynek ,thanks for reply! I'm using "S32K3XX RTD AUTOSAR R21-11 Ver 3.0.0" RTD what I use and installedRTD what I use and installed Re: s32k312 can't write dflash Hi @Vandarkholme, Which RTD version do you use? Thanks, Daniel
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RT1170 EVKB:PXP、(eLCDIF/LCDIFv2) 和 emWin 在查看了一些 PXP 驱动程序示例(即 pxp_lcdif_handshake)之后,似乎 PXP 与 eLCDIF 一起使用。 最终,我希望卸载/减少/优化用于驱动多色显示的以下 emWin 调用结构(如 emwin_gui_demo 项目)的执行时间。 if(condition) { GUI_MULTIBUF_Begin(); GUI_Exec(); GUI_MULTIBUF_End(); } 根据正在执行的图形操作,我测量了>20毫秒的执行时间,这是相当重要的。 PXP 可以与 LCDIFv2 一起使用吗?如果是的话,那么怎么办? PXP 可以与 emWin 多缓冲一起使用吗? PXP 能在多大程度上帮助卸载/减少/优化上述调用的执行时间?我还有什么其他选择(除了 GPU2D/VGLite)?
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K32W061/JN5189: 'Enhanced Frame Pending' (EFP) のスレッドサポート? 現在のNXP SDK(v2.6.13)でサポートされているThreadのバージョンはどれですか? Thread v1.2で導入されたEnhanced Frame Pending(EFP)機能を使用したいので、質問しています。 SDK で既にサポートされている場合、この機能をどのようにアクティブ化しますか?
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[Yocto][mickledore-6.1.55][iMX8MN] Marvell MV88E63930 driver crash Dear Forum, I am bringing up the driver for the Marvell switch PHY chipset (MV88E63930) in inspiring the existing device-tree of iMX8MQ and the device-tree of certain iMX6Q based board.  My custom device-tree : #include "imx8mn-evk.dts" &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; fsl,magic-packet; status = "okay"; /delete-node/ ethernet-phy@0; fixed-link { speed = <1000>; full-duplex; }; mdio { #address-cells = <1>; #size-cells = <0>; status = "okay"; switch: switch@0 { compatible = "marvell,mv88e6190"; pinctrl-0 = <&pinctrl_switch_irq>; pinctrl-names = "default"; reg = <0>; dsa,member = <0 0>; eeprom-length = <512>; reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio1>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <2>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "cpu"; ethernet = <&fec1>; phy-mode = "rgmii-id"; fixed-link { speed = <1000>; full-duplex; }; }; port@1 { reg = <1>; label = "lan1"; }; port@2 { reg = <2>; label = "lan2"; }; port@3 { reg = <3>; label = "lan3"; }; port@4 { reg = <4>; label = "lan4"; }; port@5 { reg = <5>; label = "lan5"; }; }; }; }; }; &iomuxc { pinctrl_switch_irq: switchgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 >; }; }; The switch PHY was detected so far : [ 2.293177] fec 30be0000.ethernet: Invalid MAC address: 00:00:00:00:00:00 [ 2.300008] fec 30be0000.ethernet: Using random MAC address: a2:99:6d:27:3f:a7 [ 2.308291] mdio_bus 30be0000.ethernet-1: MDIO device at address 0 is missing. [ 2.316401] fec 30be0000.ethernet eth0: registered PHC device 0 [ 8.366541] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x00 reg: 0x03 val: 0x3930 [ 8.366566] mv88e6085 30be0000.ethernet-1:00: switch 0x3930 detected: Marvell 88E6393X, revision 0 [ 8.540923] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x00 reg: 0x04 val: 0x007c [ 8.540973] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x00 reg: 0x04 val: 0x007c [ 8.540980] mv88e6085 30be0000.ethernet-1:00: p0: PortState set to Disabled [ 8.541014] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x01 reg: 0x04 val: 0x007c [ 8.541048] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x01 reg: 0x04 val: 0x007c [ 8.541054] mv88e6085 30be0000.ethernet-1:00: p1: PortState set to Disabled [ 8.541087] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x02 reg: 0x04 val: 0x007c [ 8.541121] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x02 reg: 0x04 val: 0x007c [ 8.541127] mv88e6085 30be0000.ethernet-1:00: p2: PortState set to Disabled [ 8.541160] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x03 reg: 0x04 val: 0x007c [ 8.541194] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x03 reg: 0x04 val: 0x007c [ 8.541200] mv88e6085 30be0000.ethernet-1:00: p3: PortState set to Disabled [ 8.541234] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x04 reg: 0x04 val: 0x007c [ 8.541268] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x04 reg: 0x04 val: 0x007c [ 8.541273] mv88e6085 30be0000.ethernet-1:00: p4: PortState set to Disabled [ 8.541307] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x05 reg: 0x04 val: 0x007c [ 8.541341] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x05 reg: 0x04 val: 0x007c [ 8.541346] mv88e6085 30be0000.ethernet-1:00: p5: PortState set to Disabled [ 8.541380] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x06 reg: 0x04 val: 0x007c [ 8.541414] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x06 reg: 0x04 val: 0x007c [ 8.541420] mv88e6085 30be0000.ethernet-1:00: p6: PortState set to Disabled [ 8.541453] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x07 reg: 0x04 val: 0x007c [ 8.541487] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x07 reg: 0x04 val: 0x007c [ 8.541493] mv88e6085 30be0000.ethernet-1:00: p7: PortState set to Disabled [ 8.541526] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x08 reg: 0x04 val: 0x007c [ 8.541560] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x08 reg: 0x04 val: 0x007c [ 8.541566] mv88e6085 30be0000.ethernet-1:00: p8: PortState set to Disabled [ 8.541599] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x09 reg: 0x04 val: 0x007c [ 8.541633] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x09 reg: 0x04 val: 0x007c [ 8.541639] mv88e6085 30be0000.ethernet-1:00: p9: PortState set to Disabled [ 8.541672] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x0a reg: 0x04 val: 0x007c [ 8.541706] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x0a reg: 0x04 val: 0x007c [ 8.541711] mv88e6085 30be0000.ethernet-1:00: p10: PortState set to Disabled [ 8.578945] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x1b reg: 0x00 val: 0xffff [ 8.714791] fec 30be0000.ethernet eth0: Unable to connect to phy [ 8.722167] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x1b reg: 0x00 val: 0xffff [ 8.724321] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x1b reg: 0x00 val: 0xffff [ 8.732165] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x1b reg: 0x00 val: 0xffff But it seems that there was the addr: 0x1b reg: 0x00 reading loop (please take a look at the attached dmesg log) ending up with the following messages : [ 8.714791] fec 30be0000.ethernet eth0: Unable to connect to phy [ 10.738492] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x1b reg: 0x0b val: 0xffff [ 10.738508] mv88e6085 30be0000.ethernet-1:00: Timeout while waiting for switch [ 10.745781] mv88e6085 30be0000.ethernet-1:00: ATU problem: error -110 while handling interrupt [ 10.745824] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x1c reg: 0x1b val: 0x1200 [ 10.754478] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x1c reg: 0x1b val: 0xffff [ 10.754485] mv88e6085 30be0000.ethernet-1:00: Watchdog event: 0x00ff [ 10.760896] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x1c reg: 0x1b val: 0x1300 [ 10.760940] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x1c reg: 0x1b val: 0xffff [ 10.760947] mv88e6085 30be0000.ethernet-1:00: Watchdog history: 0x00ff and a crash : [ 11.018564] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x1c reg: 0x00 val: 0xffff [ 11.018582] Unable to handle kernel NULL pointer dereference at virtual address 00000000000000dc [ 11.018842] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x1b reg: 0x04 val: 0xffff [ 11.027369] Mem abort info: [ 11.027372] ESR = 0x0000000096000004 [ 11.027375] EC = 0x25: DABT (current EL), IL = 32 bits [ 11.027379] SET = 0, FnV = 0 [ 11.027382] EA = 0, S1PTW = 0 [ 11.027384] FSC = 0x04: level 0 translation fault [ 11.027387] Data abort info: [ 11.027388] ISV = 0, ISS = 0x00000004 [ 11.027391] CM = 0, WnR = 0 [ 11.027394] user pgtable: 4k pages, 48-bit VAs, pgdp=00000000483e8000 [ 11.027398] [00000000000000dc] pgd=0000000000000000, p4d=0000000000000000 [ 11.027409] Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP [ 11.030240] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x1b reg: 0x04 val: 0xf808 [ 11.033945] Modules linked in: fsl_jr_uio caam_jr caamkeyblob_desc caamhash_desc caamalg_desc crypto_engine authenc [ 11.039375] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x1b reg: 0x04 val: 0xffff [ 11.042321] libdes overlay [ 11.045507] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x1b reg: 0x04 val: 0xf800 [ 11.050332] crct10dif_ce mv88e6xxx(+) polyval_ce polyval_generic [ 11.053304] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x1b reg: 0x04 val: 0xffff [ 11.057046] snd_soc_fsl_asoc_card snd_soc_imx_audmux dsa_core snd_soc_imx_spdif snd_soc_imx_card caam secvio error [ 11.060063] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x1b reg: 0x04 val: 0xf800 [ 11.066461] snd_soc_fsl_easrc snd_soc_fsl_sai snd_soc_fsl_spdif snd_soc_fsl_micfil [ 11.073317] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x1c reg: 0x1b val: 0x9100 [ 11.079512] gpio_ir_recv snd_soc_fsl_asrc snd_soc_fsl_utils rc_core [ 11.087038] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x1c reg: 0x01 val: 0x0000 [ 11.097424] fuse [ 11.097430] CPU: 0 PID: 591 Comm: irq/41-mv88e6xx Not tainted 6.1.55+g2cd3ece49b7e #1 [ 11.104978] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x1c reg: 0x01 val: 0x0000 [ 11.107699] Hardware name: NXP i.MX8MNano EVK board (DT) [ 11.107702] pstate: 800000c5 (Nzcv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 11.107708] pc : _raw_spin_lock_irq+0x50/0x94 [ 11.115261] mv88e6085 30be0000.ethernet-1:00: <- addr: 0x1b reg: 0x04 val: 0xffff [ 11.121275] lr : handle_nested_irq+0x24/0x144 [ 11.128802] mv88e6085 30be0000.ethernet-1:00: -> addr: 0x1b reg: 0x04 val: 0xf800 [ 11.139190] sp : ffff8000118e3ca0 [ 11.139193] x29: ffff8000118e3ca0 x28: 0000000000000000 x27: 0000000000000000 [ 11.139202] x26: ffffa883476f09c0 x25: ffffa883476f0910 x24: 000000000000003f [ 11.239219] x23: ffff10bc45c65260 x22: 00000000000000dc x21: 0000000000000000 [ 11.239231] x20: ffff10bc48622080 x19: 0000000000000001 x18: ffffffffffffffff [ 11.239244] x17: 30203a6c61762030 x16: ffffa883476f5200 x15: 2063317830203a72 [ 11.239257] x14: 646461202d3c203a x13: ffffa883493e2508 x12: 00000000000010cb [ 11.239270] x11: 0000000000000040 x10: ffffa88349452710 x9 : ffffa88349452708 [ 11.239280] x8 : ffff10bc46000270 x7 : 0000000000000000 x6 : 0000000000000000 [ 11.239293] x5 : ffff10bc46000248 x4 : ffff10bc46000270 x3 : 00000000000000dc [ 11.239305] x2 : 0000000000000001 x1 : 0000000000000000 x0 : 0000000000000001 [ 11.239321] Call trace: [ 11.239324] _raw_spin_lock_irq+0x50/0x94 [ 11.239334] mv88e6xxx_g2_irq_thread_fn+0xb8/0xfc [mv88e6xxx] [ 11.239379] handle_nested_irq+0xc0/0x144 [ 11.239389] mv88e6xxx_g1_irq_thread_work+0xd0/0x1a0 [mv88e6xxx] [ 11.239421] mv88e6xxx_g1_irq_thread_fn+0x14/0x20 [mv88e6xxx] [ 11.239456] irq_thread_fn+0x2c/0xb0 [ 11.239462] irq_thread+0x170/0x25c [ 11.239470] kthread+0x108/0x10c [ 11.239476] ret_from_fork+0x10/0x20 [ 11.239488] Code: d65f03c0 d2800001 52800022 f9800071 (885ffc60) [ 11.239492] ---[ end trace 0000000000000000 ]--- [ 11.239496] note: irq/41-mv88e6xx[591] exited with irqs disabled [ 11.246670] note: irq/41-mv88e6xx[591] exited with preempt_count 1 [ 11.368484] genirq: exiting task "irq/41-mv88e6xx" (591) is an active IRQ thread (irq 41) [ 11.584908] irq 41: nobody cared (try booting with the "irqpoll" option) [ 11.591622] CPU: 0 PID: 591 Comm: irq/41-mv88e6xx Tainted: G D 6.1.55+g2cd3ece49b7e #1 [ 11.600931] Hardware name: NXP i.MX8MNano EVK board (DT) [ 11.606244] Call trace: [ 11.608690] dump_backtrace.part.0+0xe0/0xf0 [ 11.612973] show_stack+0x18/0x30 [ 11.616293] dump_stack_lvl+0x64/0x80 [ 11.619957] dump_stack+0x18/0x34 [ 11.623272] __report_bad_irq+0x4c/0xdc [ 11.627113] note_interrupt+0x320/0x380 [ 11.630953] handle_irq_event+0x9c/0xc0 [ 11.634790] handle_level_irq+0xc0/0x1b0 [ 11.638717] generic_handle_domain_irq+0x2c/0x4c [ 11.643335] mxc_gpio_irq_handler+0x4c/0x144 [ 11.647612] mx3_gpio_irq_handler+0x94/0xf0 [ 11.651796] generic_handle_domain_irq+0x2c/0x4c [ 11.656413] gic_handle_irq+0x50/0x130 [ 11.660165] call_on_irq_stack+0x24/0x4c [ 11.664090] do_interrupt_handler+0x80/0x84 [ 11.668275] el1_interrupt+0x34/0x6c [ 11.671851] el1h_64_irq_handler+0x18/0x2c [ 11.675949] el1h_64_irq+0x64/0x68 [ 11.679354] preempt_schedule_irq+0x3c/0xd0 [ 11.683538] el1_interrupt+0x4c/0x6c [ 11.687113] el1h_64_irq_handler+0x18/0x2c [ 11.691210] el1h_64_irq+0x64/0x68 [ 11.694611] task_work_run+0xc0/0xe0 [ 11.698191] do_exit+0x2ec/0x8f0 [ 11.701426] make_task_dead+0xa0/0x19c [ 11.705178] die+0x204/0x244 [ 11.708063] die_kernel_fault+0x264/0x364 [ 11.712076] __do_kernel_fault+0x1a4/0x1ac [ 11.716177] do_page_fault+0xb8/0x360 [ 11.719840] do_translation_fault+0x9c/0xb0 [ 11.724024] do_mem_abort+0x44/0x94 [ 11.727513] el1_abort+0x40/0x64 [ 11.730744] el1h_64_sync_handler+0xd8/0xe4 [ 11.734929] el1h_64_sync+0x64/0x68 [ 11.738417] _raw_spin_lock_irq+0x50/0x94 [ 11.742426] mv88e6xxx_g2_irq_thread_fn+0xb8/0xfc [mv88e6xxx] [ 11.748212] handle_nested_irq+0xc0/0x144 [ 11.752225] mv88e6xxx_g1_irq_thread_work+0xd0/0x1a0 [mv88e6xxx] [ 11.758258] mv88e6xxx_g1_irq_thread_fn+0x14/0x20 [mv88e6xxx] [ 11.764029] irq_thread_fn+0x2c/0xb0 [ 11.767604] irq_thread+0x170/0x25c [ 11.771095] kthread+0x108/0x10c [ 11.774328] ret_from_fork+0x10/0x20 [ 11.777906] handlers: [ 11.780177] [<000000000e350f16>] irq_default_primary_handler threaded [<0000000092309199>] mv88e6xxx_g1_irq_thread_fn [mv88e6xxx] [ 11.791868] Disabling IRQ #41 Could someone share his/her experience on investigating this issue, please ? Thanks in advance and best regards, Khang i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: [Yocto][mickledore-6.1.55][iMX8MN] Marvell MV88E63930 driver crash Hi @Zhiming_Liu, As now I can configure both reset and interrupt pins in their proper logic without crash. I would like to close this ticket and with open another one to address the issue I am facing. Thanks for your support. K. Re: [Yocto][mickledore-6.1.55][iMX8MN] Marvell MV88E63930 driver crash Hi @Zhiming_Liu, I hasn't worked yet, but changing interrupts = <8 IRQ_TYPE_LEVEL_LOW>; in the initial device-tree to  interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;  helped to avoid the crash. Re: [Yocto][mickledore-6.1.55][iMX8MN] Marvell MV88E63930 driver crash Hello, Wait for your test. Best Regards, Zhiming Re: [Yocto][mickledore-6.1.55][iMX8MN] Marvell MV88E63930 driver crash Hi again, To update, I found a potential solution to enable the MDIO bit-banging as in the following discussion : https://community.toradex.com/t/mdio-via-gpio/10231/5 This MDIO bit-banging is also implemented in the existing device-tree of iMX8MQ that I shared previously. Will test and keep you up to date. 
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