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イーサネットスイッチSJA1105 SPIがデータを取得できません SJA 1105 SPIを使用してチップIDを取得すると、SDOのデータはSDIとまったく同じですが、その現象の原因は何ですか?
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GD3162ゲートドライバ こんにちはNXPの、 DESAT_LED(リーディングエッジブランキング時間)とDESATフィルタ時間の違いを明確にしてください。DESA_LEBがVdsがオンになるプログラム可能な時間を指すようにするためですか?
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Is RTD 3.0.0 compatible DMA for FlexCAN I have configured and ran a example code for receiving CAN data through DMA it does not generating any receiving complete interrupt.  Re: Is RTD 3.0.0 compatible DMA for FlexCAN Hi, yes, can be aplicable. BR, Petr Re: Is RTD 3.0.0 compatible DMA for FlexCAN MPC57xx: Configuring and Using the eDMA Controller Is this application notes totally applicable for S32K322 also? Re: Is RTD 3.0.0 compatible DMA for FlexCAN Hi @PetrS  what is the difference b/w these both functions FlexCAN_Ip_RxFifo(INST_FLEXCAN_0,&recvBuff2); FlexCAN_Ip_Receive(INST_FLEXCAN_0, RX_MB_IDX, &rxData, false); and when I was reading the k3 reference manual it was not that much clear to me, Can you provide any simple document for understand the CAN DMA , message buffer usage, CAN ID filtering, CAN Interrupts, etc. Re: Is RTD 3.0.0 compatible DMA for FlexCAN Hi @PetrS  what is the difference b/w these both functions FlexCAN_Ip_RxFifo(INST_FLEXCAN_0,&recvBuff2); FlexCAN_Ip_Receive(INST_FLEXCAN_0, RX_MB_IDX, &rxData, false); Re: Is RTD 3.0.0 compatible DMA for FlexCAN Hi, yes it is. If you have some issue please share your simplified project, or refer to posted demos, e.g.  https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-CAN-Transmit-amp-Receive-Using-MB-amp-FIFO-DMA/ta-p/1789196 BR, Petr
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GD3162 gate driver SC fault Hi NXP, What could be the reason that INTB is going to 2.5V from 5V in the case of a short circuit fault ? Can there be any causes in SW? Any possibility ? Re: GD3162 gate driver SC fault Hello Could you please let me know the result? Additionally, would you be able to test the INTB connected directly to the microcontroller? Re: GD3162 gate driver SC fault And also, INTB before connecting to micro is externally given a pull-up to 5V through a 10K resistor Re: GD3162 gate driver SC fault Hi, FYI, in our project, all the INTB pins are connected to one pin of the micro so that if any one of the gate drivers (6 gate (RH, YH, BH and RL, YL, BL) for 3 phase motor) encounters a fault, the PWM is cut off for all. In the attached image you can see that ISENSE pin of the R-L gate driver is supposed to detect phase over current cut off through SC fault and ISEN of Y-L gate driver is supposed to detect DC over current cut off through SC fault. In our case whenever ISEN of YL detects DC bus over current cut off, in that case INTB is going to 2.5V and when phase over current cut off occurs, then INTB is further transitioning from 2.5 to 0. I've noted your point to disconnect INTB from micro and check the signal again. Re: GD3162 gate driver SC fault Hello, Is the INTB pin directly connected to the microcontroller? Please note that the INTB pin has an internal passive pull-up to VDD, and INTB reports faults with an active low signal (logic 0 indicates a fault). According to the datasheet, the INTB pin should indeed be connected directly to the microcontroller. Could you confirm whether, when disconnecting the microcontroller from the INTB pin, the voltage remains at 2.5V in the event of a fault?
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リンカスクリプトの作成中にエラーが発生しました 親愛なる皆様へ 最近MCUXpresso v11.10.0に更新され、RT1024 EVKにSDK 2.15を使用しているため、FlexRAMを異なるサイズに再設定して外部RAMを削除しようとしましたが、添付の画像のようなエラーが表示されます。私はリンク https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs-Knowledge/Reallocating-the-FlexRAM/ta-p/1117649 をたどろうとしています、そしてそれはSDK 2.12とIDE v11.8の以前のバージョンで私のために働いた。何か変更が加えられ、機能しなくなったのですか? 敬具 ピング     Re:リンカスクリプトの作成中にエラーが発生しました こんにちは@ping1 , 更新情報をいただきありがとうございます。 申し訳ございませんが、 NXP の 最新の ポリシー により 、 お客様 に直接 コード を送信する ことはできません 。 NXP AN12077および https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs-Knowledge/Reallocating-the-FlexRAM/ta-p/1117649 を参照することをお勧めします。 あなたの最初の質問はリンカスクリプトの作成中のエラーについてだと思います、そして今あなたは正常にコンパイルすることができます、そしてあなたはあなたのプロジェクトの開発を続けたいと思っています、そうですか? プロジェクトが実際に外部SRAMを使用していることを確認し、HW設計に基づいてプロジェクトを開発してください。 Board_ConfigMPU設定に関しては、私はあなたのためにテストを行っただけで、MPUは設定しませんでした。あなたの実際のプロジェクトに基づいてMPUを設定してください、あなたは私があなたに投稿するリンクを参照することができます。 よろしくお願いいたします メイリュウ Re:リンカスクリプトの作成中にエラーが発生しました こんにちは、5月 FlexRAM サイズを再構成するだけでなく、ターゲット ボードに外部 SRAM がないため、外部 SRAM も削除しましたが、問題を引き起こしますか?それは私が~3年前に問題なくやっていたことです。外部RAMが主に使用されていることに気づき、後でそれを下に移動したので、代わりに内部RAMが使用されています。今のところは問題ないようですが、DTCサイズを128Kに再構成しようとはまだしていません。それを行うにはBoard_ConfigMPU()を変更する必要がありますが、あなたもそれをしましたか?あなたが私にあなたの修正したプロジェクトを送ってくれるなら、私は何が間違っていたのかをチェックできるでしょう。 敬具 ピング Re:リンカスクリプトの作成中にエラーが発生しました こんにちは、5月 あなたがしたのと同じようにダウンロードしてインストールしました - 両方のv24.12、それはあなたが言ったようにHello freertosの例で動作しますが、私がlwip_mqtt_freertos例に同じことを行うと、同じエラーが再び現れました。 緊急の助けが必要です pls 敬具 ピング Re:リンカスクリプトの作成中にエラーが発生しました ありがとう、メイ 私はIDEのいくつかのバージョンをインストールしていますが、リンカスクリプトを使用しようとすると、ロード時にどれを使用するかわかりません。 IDEv24 と SDK v24 も試してみます。 ピン Re:リンカスクリプトの作成中にエラーが発生しました 私は最初にそれを行い、v24.xxに問題があると言われたので、v11.10にロールバックしました。ところで、RT1024_connect.scpはどこにありますか? ピング Re:リンカスクリプトの作成中にエラーが発生しました こんにちは、5月 古いバージョンのSDK(2.12)とIDE(11.6)にロールバックしましたreadmeファイルによると、問題は残っています、私は問題に私の知恵を使い果たしています、それはおそらくIDEとSDKの以前のバージョンで私の他のプロジェクトの初期の段階で前に働いた。後で変更したものが何であれ、バグが発生する可能性がありますが、私が変更したことの1つは、現在freeRTOSを使用しようとしていることです。 ところで、IDE v11.10とRT1064用のSDK 2.16を使用すると、動作します。しかし、今のところ、RT1024を使用する必要があります。 敬具 ピング Re:リンカスクリプトの作成中にエラーが発生しました こんにちは、5月 SDKv2.15を使用しようとしていますが、そのためにどのIDEバージョンを使用すればよいですか? 敬具 ピング Re:リンカスクリプトの作成中にエラーが発生しました こんにちは、5月 返信ありがとうございます。 新製品を開発しており、新しいSDKとIDEバージョンを使用したいと考えています。v2.15 SDKをインストールしたばかりですが、最小IDEはv11.8であり、下位互換性があるため、それ以上のものはそれで動作するはずだと思いました。そうなんですか。 敬具 ピング
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PCA9515A evaluation environment I can't find the PCA9515A EVK, but is it possible to replace the PCA9515ADP with the PCA9617ADP-ARD (URL below) and evaluate it? If there are any points to note, would you let me know? https://www.nxp.jp/design/design-center/development-boards-and-designs/analog-toolbox/arduino-shields-solutions/pca9617adp-ard-arduino-shield-level-translating-fm-plus-ic-bus-repeater-evaluation-board:PCA9617ADP-ARD Re: PCA9515A evaluation environment Hi Jozef, Thank you very much for your kind reply. My question was solved. Best regards, Bata Re: PCA9515A evaluation environment Dear Kawabata-san, the PCA9617A is more advanced, than the PCA9515, although these two are very similar. But what will work on the PCA9617A, might not work on the PCA9515. Yes, I would recommend you to use the PCA9617ADP-ARD, but then please consider also use the PCA9617A for your application.  With Best Regards, Jozef
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where to find S32S info Hello, In the link below https://www.nxp.com/docs/en/white-paper/GREENBOX2WPA4.pdf it shows "S32S" but from the list of "S32 Automotive Platform Processing Products" in below page https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform:S32 I cannot find any link or word about S32S. Do we have a chip named S32S or it is just a collection of S32 family, i.e a plural of S32?? Thanks Re: where to find S32S info Hi, What we are referring to is that links available under nxp.com related to S32S will redirect to S32Z, similar to the one shown below (which was the S32S product page under NXP): https://www.nxp.com/S32S Please, let us know. Re: where to find S32S info Hello, Thanks for the finding. However can you specify which one can redirect to S32Z/E? For example, I cannot see below "S32S" is same as "all S32S links do redirect to the S32Z/E products...." Thanks Re: where to find S32S info Hi, We can confirm that, under the documentation you have provided and manual searching from our side, all S32S links do redirect to the S32Z/E products. Please, let us know. Re: where to find S32S info Can you help confirm "S32S2 microcontrollers are redirected to the S32Z or E family products" So I can further know who I should contact. Re: where to find S32S info Hi, Seems to be that all information regarding S32S2 microcontrollers are redirected to the S32Z/E family products. For more information on regards of the latter, help us contacting your local NXP FAE/DFAE/representative, since at this moment all documentation is under control of distribution. Please, let us know.
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NTAG I2C Pass-through with CLRC663 I am trying to test passthrough mode using NTAG-I2C+ dev kit for Arduino (OM23221ARD) to a CLRC663 reader running the SW297859 SDK, but have been unable to get any data written from the CLRC663 to the NTAG's SRAM buffer in passthrough. I've run the NfcrdlibEx9_NTagI2C example in SW297859 and this confirms that pass through is enabled on the NTAG. I've tried updating this block (see attached) to perform an ISO14443 exchange with the NTAG but the SRAM_I2C_READY of the NS_REG never gets set and if I dump the SRAM I don't see anything written. On the CLRC663 side I get a 0x201 error which looks like a timeout on waiting for a response (which makes sense since I don't currently have the NTAG sending anything back until the SRAM_I2C_READY gets set). Attached is the code change that I made. Can someone please point me the correct direction for performing an ISO14443 exchange with the NTAG? Or is it even possible to perform passthrough exchanges with the CLRC663 running SW297859 SDK since it doesn't support P2P? NFC Frontend Solutions Re: NTAG I2C Pass-through with CLRC663 Hi Fabian, Thanks for your help on this. We got bi-directional communication working with the fast-write commands using the CLRC663 and an Arduino connected to the NTAG. Attached are the code snippets that might save someone else some time in the future. Jeremy Re: NTAG I2C Pass-through with CLRC663 Hello sir, I believe this snippet from the Example may be helpful. Even if the implementation isn't for Pass-through. Unfortunately, as I mentioned we don't have an implementation at this moment as an example to share. My apologies for this. If you could please try using the Mful_fastRead() and the sector select. Which in this case would be sector 0. If you are having issues with the implementation please do not hesitate to share it with us to provide further support. Re: NTAG I2C Pass-through with CLRC663 I don't thing there is any issue with my configuration of the NTAG since I can see it working using the NXP Android reference app when I write to the NTAG then read back over I2C. I believe there is something I am missing on the CLRC663 side of things. I have tried phalMful_FastWrite() without success. Could you provide reference code of using phalMful_FastWrite() that I could use as a starting point? Re: NTAG I2C Pass-through with CLRC663 Hello sir, Unfortunately, we don't have the specific implementation using phpalI14443p4_Exchange() since the implementation in the Ex9_NTagI2C example is using the MIFARE Ultralight API for performing T2T interfacing, we recommend please adopt this practice as well. As recommended in the Datasheet, please use the FastRead command. The MfUl does have this function as: phalMful_FastRead() I'm sure you already have checked SW3647 and SW3648. But in SW3647, NTAG_I2C_Explorer_Demo is shown in CopyInterruptToSRAM() how we recommend copying the data into the SRAM for the CLRC663 to be able to read the passed values. In SW3648, there is a file called Ntag_I2C_Demo which shows the implementation for reading into the SRAM. It is required to check if the SRAM is ready before starting to read the actual memory since it could be blocked from the NFC side. I hope this information may be useful sir. Re: NTAG I2C Pass-through with CLRC663 I can get passthrough working using the NXP sample app for Android (not for iOS) so this implies the NC_REG is set correctly on the NTAG side. What I can't get working is the CLRC663 writing to NTAG via passthrough. void enablePassThroughRFToI2C() { // From NFC SDK // NTAG_SetTransferDir(ntagCoreStateHandle.ntagDriverHandle, RF_TO_I2C); { // ntag.writeRegister(Ntag::NC_REG, NTAG_NC_REG_MASK_PTHRU_ON_OFF, 0); ntag.writeRegister(Ntag::NC_REG, NTAG_NC_REG_MASK_TRANSFER_DIR, RF_TO_I2C); ntag.writeRegister(Ntag::NC_REG, NTAG_NC_REG_MASK_PTHRU_ON_OFF, 0x40); } For the CLRC663, as seen in the previous code snippet, I am prepending the APDU with: uint8_t writeSRAMCmd[] = {0xA6, 0xF0, 0xFF}; // Fast write to Start address of the SRAM block ..but this is not working. Could you provide sample code snippet for CLRC663 writing to the NTAG SRAM buffer? Re: NTAG I2C Pass-through with CLRC663 Hello sir, Thank you for sharing this code snippet. In order to implement the RF -> I2C writing, it is required to first serve the correct direction, and the FD pin in NC_REG. Please share this register configuration to double-check if this is correct. Please keep in mind that this configuration has to be done through I2C. The implementation of the start and end addresses looks good. I believe that the issue is with the register configurations, sir. Could you please check NC_REG values while in session? It is recommended to please implement a CRC when writing to the SRAM directly. Re: NTAG I2C Pass-through with CLRC663 I have tried variations of this with no success. For reference on the NTAG is powered from VCC and I can see data get written to SRAM successfully when using the Android NTAG I2C app so I believe my issue is isolated to what I am doing on the CLRC663. I am using the `./SW297859/Examples/NfcrdlibEx9_NTagI2C` example with the only change to the if block that deals with an NTAG in passthrough: /* check for Pass-through mode */ if ((bDataBuffer[0] & PTHRU_ON_OFF)) { LOG_DEBUG("Writing to NTAG"); uint8_t writeSRAMCmd[] = {0xA6, 0xF0, 0xFF}; // Fast right to Start address of the SRAM block uint8_t dataToWrite[] = {0xDE, 0xAD, 0xBE, 0xEF}; // Example data uint8_t sramWrite[sizeof(writeSRAMCmd) + sizeof(dataToWrite)]; memcpy(sramWrite, writeSRAMCmd, sizeof(writeSRAMCmd)); memcpy(sramWrite + sizeof(writeSRAMCmd), dataToWrite, sizeof(dataToWrite)); status = phpalI14443p4_Exchange(pHal, PH_EXCHANGE_DEFAULT, sramWrite, sizeof(sramWrite), NULL, 0); CHECK_STATUS(status); From the log statement I can see that we attempt to write something, but nothing shows up on the NTAG. I have tried manually appending a CRC as well as writing a full 64 bytes, but have been unable to get anything written. Could you give sample code of how I can write anything to the SRAM buffer? Re: NTAG I2C Pass-through with CLRC663 Hello sir, Yes the CLRC663 does support Ntag I2C passthrough. The issue is that the example from the NFC Reader Library is only, reading specific pages of the NTAG I2C. Once the passthrough is enabled in the NTAGI2C, the CLRC663 needs to read directly to sector 0, page address 0xF0. As mentioned in section 11.3.1 the use of Fast Read commands are recommended. Please keep in mind that both interfaces cannot be accessed at the same time and the status registers need to be implemented in your application using NS_REG. Also, keep in mind that in order to access SRAM is required to power on the device via VCC Unfortunately, we don't have a specific implementation for this in the Library examples. If you could please share your application output and/or implementation. We may be able to provide further help. Re: NTAG I2C Pass-through with CLRC663 Yes, I have looked at AN11579 and can get pass through working between the demo phone app and NTAG but not when using the CLRC663 as the Reader. It would be very helpful if you could tell if the CLRC663 is capable of pass through communications with NTAG I2C Plus to begin with? Re: NTAG I2C Pass-through with CLRC663 Hello, my name is Fabian, I've been assigned to support your case. Thank you for your interest in our products I'm not sure if you have already checked AN11579 is explains the respective configurations and some Block communications schemes for data transfer depending on the requirements of your project. At this point, it is difficult to detect what is wrong with your setup. Please help us by trying to follow the mentioned schemes and let us know if you are still having issues.  Please keep in mind that is very important to configure FD_ON and FD_OFF and get it's status while in session to correctly access the IC through the interfaces. Please let me know if this information is helpful.
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[iMX8M Nano] Using General Purpose Timer (GPT) to Count the external Signal Pulses Question:  What is the maximum rising time of external GPT_CLOCK signal? The Problem: We are using iMX8 Nano CPU…We want to use GPT TIMER to count the pulse of external signal…we configure UART3_TXD pad (D18) as GPT1_CLK function and connect our external clock to this pin. We can see the GPT Counter count this signal. However, this only works with simulated signal with rising time about 50ns (see the below picture). When we inject the real signal with rising time about 250ns…the GPT does not count. I use devmem2 tool to access the register directly as below: Set Custom Pin (0x30330248) as GPT1_CLOCK: 0x00000003 Set Clk Select (0x303305E8) to select external clock which is GPT1_CLK: 0x00000001 Set counter mode via Control Reg (0x302D0000): 0x000000C3 Read the Counter value via Count (0x302D0024) Compare the two rising edges of the two signal pulses The Green Line is the simulated signal The Mint Blue is the real signal i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: [iMX8M Nano] Using General Purpose Timer (GPT) to Count the external Signal Pulses Hello @Coeus412  Please be sure that this condition is achaiving: The GPT counter can be operated using an external clock from outside the device, and this is the input pin used for that purpose. The external clock input (GPT_CLK) is treated as asynchronous to the peripheral clock (ipg_clk). To ensure proper operations of GPT, the external clock input frequency should be less than 1/4 of frequency of the peripheral clock (ipg_clk). Hysteresis characteristics on this pad will be required because this is a clock input. (From reference manual 12.1.2.1 External Clock Input) Best regards, Salas. Re: [iMX8M Nano] Using General Purpose Timer (GPT) to Count the external Signal Pulses I notice when we use the simulated signal generated by another GPIO of IMX8 the GPT Counter can count correctly (even though the rising time 250ns same as real signal) …but it does not count the real signal. I am checking the datasheet and found below block diagram (there is Sync block with ipg_clk). Does it mean the external GPT_CLK signal need to synchronize with ipg_clk?
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unable to use simulink s32 configuration in S32 Design Studio (S32DS) due to version mismatch Hi, I have a Simulink project which I'm trying to debug in S32DS. The code builds, runs, and I can debug, but I'm not able to view (or edit) the configuration in S32DS. I get the attached error. Do I need to install an additional addon version or how can I resolve this? Re: unable to use simulink s32 configuration in S32 Design Studio (S32DS) due to version mismatch Hi, @Deskwork4130 , The newly added S32K3 Toolbox version 1.5.0 is compatible with: - S32 Configuration Tools version 2024.R1.7 - S32 Design Studio version 3.5 Please try this setup with the most recent toolbox version and let us know if you still have issues with Design Studio integration. Hope this helps, Dragos Re: unable to use simulink s32 configuration in S32 Design Studio (S32DS) due to version mismatch the release notes of 1.5 refer to configuration tools version v2021.R1.7. release notes for 1.4 has v2021.R1.6. so this seems like a very minor change. what version of S32DS is compatible with this version of config tools? as a side note for anyone looking in the flexnet SW center v1.5 is not in the same place as the previous versions. it is in the generic MBDT not the S32K3 specific one for some reason. Re: unable to use simulink s32 configuration in S32 Design Studio (S32DS) due to version mismatch Hi, @Deskwork4130 , We just published the MBDT for S32K3 Toolbox version 1.5.0. Installing this version and running the debug again is what I advise.  Let us know if your problem persists. Best regards, Dragos
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The K344 uses polling to capture PWM duty cycles (emphasis: no interruptions) I want to use 344MCU to capture a way of PWM duty cycle, it seems that only with interrupts + SAIC mode to achieve duty cycle capture, but I can not use interrupts. I figured out if I could configure two pins, one pin to capture the pulse width (IPWM mode) , the other pin to capture the pulse frequency (IPM mode) , then connect the two pins together and then connect the PWM waveform to be captured, ah, with the pulse width and pulse frequency to get the duty cycle. What I don't understand is that if I connect the two pins of the MCU together, will the two pins interfere with each other while capturing the PWM signal? Re: The K344 uses polling to capture PWM duty cycles (emphasis: no interruptions) Sorry, I just noticed the message now. Here is the program provided by technical support, but it should still be the interrupt capture PWM duty cycle method. The actual implementation using polling can be seen in my solution below, which has been verified. Re: The K344 uses polling to capture PWM duty cycles (emphasis: no interruptions) I tested the example, found that the PWM cycle and duty cycle can be obtained under interruption conditions. Afterwards, I regenerated the code and removed the interrupt enable and interrupt interface. In non interrupt situations, both the cycle and duty cycle were returned as 0. In addition, I use IPWM and IPM to capture a PWM signal (two pins). IPWM obtains a high level, IPM obtains a cycle, and the duty cycle can be obtained without any interruption.I think this is the only way to obtain the PWM duty cycle without any interruption. Here is my approach: 1.Pin settings: 2.Emios_Mcl_Ip: 3.Emios_Icu: 4.demo init ipwm and ipm: 5.demo get duty: Re: The K344 uses polling to capture PWM duty cycles (emphasis: no interruptions) Hi Have you already referred to S32K344_Example_Emios_Icu_IPWM_measurement_DS34_RTD_100_v2?  If you want to use polling method instead of interrupt method, please poll the status via Emios_Icu_Ip_GetInputState before calling Emios_Icu_Ip_GetDutyCycleValues. Since I don't know the S32K3 RTD version you are using, I sent you the S32K344_Example_Emios_Icu_IPWM_measurement_S32DS35_RTD400.zip through private message. It is recommended to modify it to the polling mode based on project. Sorry, I haven't had time to test the polling method for you because I have been dealing with a lot of cases recently. If you still can't implement it after the modification, please let me know. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
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Yocto NXP GA release and meta-freescale mismatch Hi, I am working on upgrading Linux for an old HW platform using i.MX6UL. I am trying to freeze a version/tag/commit for the Yocto meta-imx and meta-freescale. But I found version mismatch when I refer to GA release when bitbake firmware-imx. I have put all the detailed steps and logs in README in this repo. scarthgap-6.6.23-2.0.0  scarthgap-6.6.36-2.1.0  Please follow these two branches to re-produce the problem described in the "Known issue" section: scarthgap-6.6.23-2.0.0 known-issue  scarthgap-6.6.36-2.1.0 known-issue  Please help to look at this issue. Thanks in advance! BR/Chencheng i.MX6UL Yocto Project Re: Yocto NXP GA release and meta-freescale mismatch Hi Chavira, I bumped all the meta layers to use imx GA 6.6.52 2.2.0 release. And this particular issue is gone. BR/Chencheng Re: Yocto NXP GA release and meta-freescale mismatch Hi @securemetersczhang! Thank you for contacting NXP Support! Unfortunately we can't do nothing since is not an official repo. Please download the source code from the official NXP repository. Best Regards! Chavira
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s32k144 MCALプロジェクトでウォッチドッグモジュールをデバッグする際にWdg_Wdog0_Isr()割り込みを入力できない問題について 皆さん、こんにちは。S32K144ウォッチドッグモジュールをデバッグしている際、MCUをリセットする前にWdg_Wdog0_Isr()割り込みを入力するのが適切です。しかし、デバッグプロセス中に、MCUをリセットする前にWdg_Wdog0_Isr()割り込みを入力していませんでした。以下は私のS32DSプロジェクトとEB設定です。問題箇所を特定していただけますか?ご協力ありがとうございます! Re: s32k144 MCALプロジェクトでウォッチドッグモジュールをデバッグするときにWdg_Wdog0_Isr()割り込みを入力できない問題 わかりました。ご回答ありがとうございます。感謝します。 Re: s32k144 MCALプロジェクトでウォッチドッグモジュールをデバッグするときにWdg_Wdog0_Isr()割り込みを入力できない問題 こんにちは。ご回答ありがとうございます。ウォッチドッグモジュールに関する私の理解は少し偏っているかもしれません。私の理解では、Wdg_SetTriggerCondition()関数で設定されたタイムアウト期間内にウォッチドッグにフィードが供給されない場合、つまりWdg_SetTriggerCondition()が再度呼び出された場合、ウォッチドッグ割り込みがトリガーされ、その後割り込みが生成されます。その後、インターネット上のブログ(図に示すように)で、割り込みモードでは、ウォッチドッグに最初のフィードが間に合わないとウォッチドッグ割り込みが生成され、2回連続してウォッチドッグフィードがタイムアウトした後にのみMCUがリセットされると書かれていました。どちらが正しいのか教えていただけますか? Re: s32k144 MCALプロジェクトでウォッチドッグモジュールをデバッグするときにWdg_Wdog0_Isr()割り込みを入力できない問題 こんにちは!以前のモジュールはすべてこのバージョンに基づいて構成されており、残っているモジュールは1つか2つだけです。今後S32K3シリーズのチップを使用するときは、最新のMCALバージョンに切り替える予定です。現状では、プログラムの電源投入後、一定時間ごとにライトが1回点滅します(非常に速く点滅します)。ただし、下図のように、ウォッチドッグ通知機能に遅延機能を追加しましたが、それでもライトは非常に速く点滅します。(この遅延機能をメイン関数でテストしたところ、このライトの点滅速度よりも明らかに遅いです)。原因は何でしょうか? Re: s32k144 MCALプロジェクトでウォッチドッグモジュールをデバッグするときにWdg_Wdog0_Isr()割り込みを入力できない問題 こんにちは。プログラムを数回実行し、実行状態にしたところ、割り込みでプログラムが常に停止してしまうことがわかりました。通知に点滅ライトのコードを追加すると、ライトが常に点灯していることがわかりました。S32DSの一時停止ボタンをクリックすると、プログラムは下図の位置で停止し、ライトが消灯します。原因の分析を手伝っていただけますか?設定の問題でしょうか? Re: s32k144 MCALプロジェクトでウォッチドッグモジュールをデバッグするときにWdg_Wdog0_Isr()割り込みを入力できない問題 こんにちは。ご指摘のとおり、Wdgの割り込み通知機能にライトオン動作を追加したところ、ライトオン現象を確認できるようになりました。上記の通り、EB設定で「Wdg Runs In Debug Mode」オプションを無効にしても、S32DSでデバッグ中にWDOGのCNTレジスタの値が増加することがあります。設定に何か問題があるのでしょうか? Re: 关于s32k144 MCAL项目中调试看门狗模块进不了Wdg_Wdog0_Isr()中断的问题 Hi @夏超  通常、遅延やコードをコールバック関数内に直接配置することは、パフォーマンスと応答性に影響を与える可能性があるため、お勧めしません。ただし、次のような実装を試みることもできます。 #define NUM_OF_NOTIFICATIONS 10U #define TIMEOUT_WDG 5000U uint8 count = 0U; int main(void) { ... Wdg_SetTriggerCondition(TIMEOUT_WDG); hile (count < NUM_OF_NOTIFICATIONS) { /* Set the Trigger Condition after the Wdg notification is called */ if (NotificationCount == 1U) { Wdg_SetTriggerCondition(TIMEOUT_WDG); Dio_WriteChannel(DioConf_DioChannel_RGBLED0_BLUE, STD_HIGH); delay(TIMEOUT_WDG / 5); Dio_WriteChannel(DioConf_DioChannel_RGBLED0_BLUE, STD_LOW); count++; u8NotificationCount = 0; } if (count == 9) { Wdg_SetTriggerCondition(TIMEOUT_WDG); Dio_WriteChannel(DioConf_DioChannel_RGBLED0_GREEN, STD_HIGH); } } ... } このコード例では、各通知の受信後にトリガー条件を設定し、それに応じて LED ステータスを更新します。遅延(TIMEOUT_WDG / 5)は、短い遅延を作成するために使用されますが、理想的には、コールバック関数内の問題を回避するために、これをノンブロッキング方式で処理する必要があります。 Re: 关于s32k144 MCAL项目中调试看门狗模块进不了Wdg_Wdog0_Isr()中断的问题 Hi @夏超  デバッグ セッション中で、ウォッチドッグをデバッグ モードで実行できるようにしない場合、WDG カウンタはインクリメントされません。その結果、タイムアウト値に到達せず、したがって割り込みはトリガーされません。 実行時に割り込みがトリガーされるかどうかを監視するには、割り込みが発生するたびにLEDを点滅させるなどの簡単な方法を使用できます。これにより、割り込みが正しく実行されていることを視覚的に確認できます。 Re: 关于s32k144 MCAL项目中调试看门狗模块进不了Wdg_Wdog0_Isr()中断的问题 Hi @夏超  ウォッチドッグをデバッグ モードで実行できるようにすることで、デバッグ セッション中に WDG カウンターがカウントを続行できます。これは、割り込み関数が正しく呼び出されていることを検証するのに役立ちます。ただし、WDG が有効になると、そのカウンタは増加し続けます。ブレークポイントにヒットするか、[ステップ オーバー] オプションを使用すると、WDG カウンターがオーバーフローし、リセット要求がトリガーされます。 BR, VaneB Re: 关于s32k144 MCAL项目中调试看门狗模块进不了Wdg_Wdog0_Isr()中断的问题 谢谢您的回复!但当我失能Wdg Runs In Debug Mode这个选项,Wdg_Wdog0_Isr()还是不能进入,能否进一步帮我分析下原因,谢谢您了! Re: 关于s32k144 MCAL项目中调试看门狗模块进不了Wdg_Wdog0_Isr()中断的问题 Hi @夏超  申し訳ございませんが、画像は添付されていないようです。再送していただけませんか?さらに、古いソフトウェアバージョンを使用していることに気づきました。最新バージョンをテストして、問題が解決しないかどうかを確認するのを手伝ってもらえますか? 最新のソフトウェアリリースは、 Real-Time Drivers for S32K1 → Automotive SW - S32K1_S32M24x - Real-Time Drivers for Cortex-M からダウンロードできます。
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Running LIN Demo and Free master together possible? I want to use the LIN demo example and use it to demonstrate on Freemaster, I just got to know that both things use the same LPUART peripheral that inst 2. what to do? Re: Running LIN Demo and Free master together possible? Hi, Thank you so much for your interest in our products and for using our community. For your previous tickets, I assume that you are using S32K144EVB. If not please tell me. In S32K144EVB, LIN Phy is connected to LPUART2, while OpenSDA is connected to LPUART1, the last one is commonly used to connect to FreeMASTER thought the Micro USB connector. On the other hand, you can customize SW to connect FreeMASTER to any LPUART instance or even CAN. Additionally, you can customize your HW to connect LIN Phy to any LPUART instance. Hope it helps you. Have a nice day!
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How many pins FLEXIO_SPI needs? Hi NXP Team, I'm looking for a configuration of SPI on a S32K358 board using FLEXIO module. I was wondering if it needs 4 pins with the FLEXIO feature or less. Thanks, Simon Re: How many pins FLEXIO_SPI needs? Hi, Thank you so much for your interest in our products and for using our community. You need 4 pines, please refer to Lpspi_Flexio_Ip_Transfer_S32K358 project example. Hope it helps you. Have a nice day!
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rpmsg examples not working on SDK_24_12_00_EVK-MIMX8MP Hi guys. There seems to be a problem with the 2 multicore examples with version 24.12 or the IMX8MP SDK. Both the pingpong and the echo don't work. When I first try to build them, VSCode complains about missing the include file "freertos_tasks_c_additions.h" in task.c. If you change FreeRTOSConfig.h line 66 to #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 (basically, remove the include in task.c), then it compiles, but when you try to run the .elf from the Linux side, all you get is "echo: write error: Invalid argument" and nothing works. Eventually you get stuff like kernel panics.   It was driving me crazy trying to fix it (the basic hello world examples I compiled worked just fine, and the pre-compiled .elf in the Yocto build worked just fine), so I tried going back to SDK version 2.16 and low and behold, everything worked on the first try.   So, yeah, there's very likely something wrong with these 2 examples (maybe others too) in SDK_24_12_00_EVK-MIMX8MP.   Just wanted to let you know, you might wanna fix this. Re: rpmsg examples not working on SDK_24_12_00_EVK-MIMX8MP Hello, Have reported this issue. Best Regards, Zhiming
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Obtaining shortest FMPLL timing possible, with MPC5634M Have a fairly small Development Application (<3kB), Safety Critical.  Currently running on a TRK-MPC5634M Demo Board. Requirement is for the Function start to execute, as close to MCU Power-up, as is possible.  Wanting to shorten the time FMPLL takes to complete, to an absolute minimum. The FMPLL Coding, is based upon the helpful "AN11960.pdf" Document. A stepped approach was employed, safely affording some overshoot of the initial 64MHz Clock, before stepping to the maximum 80MHz Frequency for the MPC5634M Device. This final Frequency could likely be lowered (say to 64MHz), if the FMPLL could be accelerated.  With a lower initial Clock (say 40MHz, or even 32MHz). It would appear that the "FMPLL.ESYNCR1.B.EMFD" setting might affect how aggressively the FMPLL is able to lock, in terms of time taken. Here's the complete FMPLL Implementation: // Disable clock monitoring flags (loss of Lock, Clock Reset & lock IRQ) FMPLL.ESYNCR2.R = 0x00000000; // Disable PLL. Clock Mode bypass of 8MHz Crystal Reference. FMPLL.ESYNCR1.B.CLKCFG = 0x01; // Configuration set to Enhanced Mode. FMPLL.ESYNCR1.B.EMODE = 0x1; // Setup ERFD PLL Ramping Step to minimum value of zero (divide by 2) FMPLL.ESYNCR2.B.ERFD = 0x0; // Setup EPREDIV Enhanced Divider to 4 (divides 320MHz VCO by 5) to // target initial 64MHz Clock.  FMPLL could safely overshoot this (some). FMPLL.ESYNCR1.B.EPREDIV = 0x04; // Enhanced multiplication factor-divider. Divides by 40, here. // Not sufficiently explained how this works.... FMPLL.ESYNCR1.B.EMFD = 0x28; // Set Clock Mode to Bypass, Crystal Ref. and PLL on. FMPLL.ESYNCR1.B.CLKCFG = 0x03; // Wait for intermediate 64MHz Frequency to lock. N.B. The LOCK bit is b28. while (FMPLL.SYNSR.B.LOCK == 0) {} // Update EPREDIV Enhanced PRE-DIVider to 3 (divide 320 MHz VCO by 4). // // Selects the final target Frequency at nominal MPC5634M 80Mhz maximum. FMPLL.ESYNCR1.B.EPREDIV = 0x03; // Configure Clock as normal with Crystal Reference FMPLL on, to complete. FMPLL.ESYNCR1.B.CLKCFG = 0x07; Re: Obtaining shortest FMPLL timing possible, with MPC5634M Thanks for that Information. I had hoped that the POR period might have been extended on the TRK-MPC5634M Board.  Was using one to measure Timings on a 'Scope shortly after entry into main() (immediately after initializing GPIO Ports and asserting outputs captured via P5 eMIOS Pins), and again after a two Stage PLL to 80MHz, completed. It is for a Control Application, driving and monitoring custom Electronics. Not likely to be a problem, for Automotive use! Re: Obtaining shortest FMPLL timing possible, with MPC5634M Hi @andydcoles, Unfortunately that is not possible, you cannot modify the POR timing it is required to follow the default POR sequence in order to have a successful boot. Regards Re: Obtaining shortest FMPLL timing possible, with MPC5634M Hi SebastianG PLL doesn't appear to be that slow, compared to typical MCU PoR. The reason I ask, is for a Control Application that needs to start, ASAP. We'd likely get more mileage out of shortening PoR duration, to the lowest recommended value. Best Regards Andrew Re: Obtaining shortest FMPLL timing possible, with MPC5634M Hi @andydcoles, Could you please share with me a log with the results of your implementation? Regards Re: Obtaining shortest FMPLL timing possible, with MPC5634M Hello @andydcoles, I'm working on your question, When I have any update I will let you know Regards
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How to add u-boot-fw-utils tools into LLPDUG based on LX2160ARDB_REV2 Hi, We need fw_printenv and fw_setenv tools on LX2160ARDB, LLPDUG version we are using 5.15.71, but I cannot find the u-boot-fw-utils bb file Do you have any suggestions? BR, Jack Ho   Re: How to add u-boot-fw-utils tools into LLPDUG based on LX2160ARDB_REV2 Please add "libubootenv" in variable IMAGE_INSTALL in meta-nxp-desktop/recipes-fsl/images/ls-image-main.bb, then run "bitbake ls-image-main".
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Accessing specific PWM channel in Linux Hi, I am trying to access a specific channel, channel 5 of the PWM1 output from flex_timer_1 on the S32G274. I am not sure what values to use on the command line or settings in the dts file in order to obtain an output? In my dts file, I have the following: myboard.dts   &pwm1 {     pinctrl-names = "default";     pinctrl-0 = <&pwm1_out_pins>;     status = "okay"; };   &pinctrl {      pwm1_out_pins: pwm1_out_pins {           pwm1_out_grp {               pinmux = ;               output-low;               output-enable;               slew-rate = ;   // Is this needed?          };     }; };   Then, when I run the following commands on the Linux command line:   echo 1 > /sys/class/pwm/pwmchip0/export echo 10000000 > /sys/class/pwm/pwmchip0/pwm1/period echo 5000000 > /sys/class/pwm/pwmchip0/pwm1/duty_cycle echo 'normal' > /sys/class/pwm/pwmchip0/pwm1/polarity echo 1 > /sys/class/pwm/pwmchip0/pwm1/enable   I don't receive any errors, but I do not see an output on PF_00, pin for PWM1, channel 5. I'm not sure if the /sys/class/pwm/pwmchip0/export file controls the output channel? I did try    echo 4 > /sys/class/pwm/pwmchip0/export   but received an error.   Is there something I need to add in the dts file in order to access channel 5 of flex_timer_1 for PWM1? Or is there a command I need to execute on the command line to provide the PWM output?   Thanks for any assistance.   Re: Accessing specific PWM channel in Linux I found the problem. It was the wrong channel assignment. Note, for channel PWM5, use: echo 5 > /sys/class/pwm/pwmchipio/export. I was using channel 4 since the PWM starts with one apparently and not with zero. If in your kernel driver, the setting would be pwm_device = pwm_request( , ). So, for example, to obtain channel 5 with PWM0 enabled, it would be: struct pwm_device *my_pwm_device; my_pwm_device = pwm_request(5, pwmchip0); Thanks for the help. Re: Accessing specific PWM channel in Linux Thank you for the assistance so far. After reviewing the examples and delving into the links, I saw that I am doing pretty much the same thing as the example for imx8mmn-nitrogen8mm.dtsi example. I did notice that if I do the following command, "echo 4 > /sys/class/pwm/pwmchip0/export," I do see "/sys/class/pwm/pwmchip0/pwm4."  But I am still not sure how to set the channel in the dts file?  Also, with pin 80 set for PWM5 output through the dts file pinmux, I still do not see any PWM on the output pin either.  Do I have to create a "PWM5" entry in the dts file for channel 5 of the PWM? If so, would I have to clone parameters from PWM1 in the s32cc.dtsi file? Is there an example of this? I could not find anything is my extensive search online. Thanks again. Re: Accessing specific PWM channel in Linux Hi @Tony-FM-Eng,  Thank you very much for your response. Based on your reply and your steps described on your question, Linux can interface correctly PWM driver. However, it seems that you are missing a Kernel configuration to properly set up the PWM. I couldn't find any specific manual for the S32G to enable PWM but please have a look to the following community thread of i.MX8MM Solved: Q: What is the preocedure to Enable PWM on imx8mm-evk? - NXP Community. Please check and tell me if you have any questions or comments. Re: Accessing specific PWM channel in Linux Thanks for the reply. Here are the following outputs to the commds: # ls /sys/class/pwm pwmchip0 # ls /sys/class/pwm/pwmchip0 device export npwm power pwm1 subsystem uevent unexport # ls /sys/class/pwm/pwmchip0/pwm1 capture duty_cycle enable period polarity power uevent Let me know if you require any additional information. Re: Accessing specific PWM channel in Linux Hi @Tony-FM-Eng,  Thank you for contacting NXP Support. It seems that the configurations are correct. Could you please share the output of the following commands? ls /sys/class/pwm/ ls /sys/class/pwm/pwmchip0/ ls /sys/class/pwm/pwmchip0/pwm1 Please try it and send me the outputs. Have a great day!
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如何获取此材料的 ESD 性能信息?BAP64-02 我已经在 NXP 网站上搜索了有关该组件的所有文档。好像没有找到相应的描述。您能帮我找到这些信息吗? 射频 回复:如何获取此材料的 ESD 性能信息?BAP64-02 由于我们不会公开分享此类数据,因此我们通过电子邮件回答了这个问题。
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