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What kind of port does the T Embed have? I have the standard model T Embed, but i have no Idea what kind of port it has (the other port, not usb c), because the official site says its a grove port, the lilygo Wiki site says its a qwiic port. Can anyone help me please?
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Compatibility of Camera module with OX05B1S Sensor and in-built ISP with i.MX95 FRDM Hi All, Want to know if camera module with ox05b1s sensor and in-built ISP (similar to 5MP RGB-IR Global Shutter GMSL2 Camera for NVIDIA Jetson AGX Orin would be compatible with i.MX95 FRDM board). I do understand that i.MX95 only have MIPI_CSI2 port hence I need to find GMSL2 to MIPI_CSI2 converter, however my question is specifically related to compatibility of existing driver that is part of NXP Linux BSP. Will driver Camera driver of NXP Linux release directly work with this camera module? Do I need to make modification in dtb file? Any other modifications would or additional work that I need to plan for?
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M&P Multilink I have developed approximately 20 projects using S08 processors and CodeWarrior 11.1  with the P&E Multilink Universal FX debugger. I used an Intel-based MAC with Parallels VM running Windows 7. Everything worked Great! I now have a new MAC , again running Parallels VM and Windows 11. (no choice). CodeWarrior loaded, but with a message about no device driver. It works fine, but the debugger is not recognised. On the old Mac, Windows Device Manager showed an entry "Jungo Connectivity/Windriver", but on the new MAC the device manager only showed an entry "MULTILINK".  There are a number of suggested fixes but the proposed files could not be found, Can someone please offer me a working solution, even if it means using a different debug probe. Re: M&P Multilink If you update from Windows 7 to Windows 11, all the related driver may need to reinstall CodeWarrior® for MCUs (Eclipse IDE) could be a good choice to select CodeWarrior® for MCUs (Eclipse IDE) - ColdFire®, 56800/E DSC, Qorivva® 56xx, RS08/S08, S12Z - 11.1 Re: M&P Multilink I hate Windows and I am not updating from W7 to W11 - it is a new machine (Mac M4) and W7 is not compatible so I have no choice.I have been using CodeWarrior for about 25 years. My question was "which drivers do I need for W11 and where can I find them?  Just as a point of interest and nothing to do with this topic, AUTODESK products will no longer run on old Intel-based Macs, so Windows 7 - R.I.P. Re: M&P Multilink Hello, I would recommend on using the OS windows 11 for using CodeWarrior v11.1 this is the supported option, not virtual machines; as we can't guarantee that the CodeWarrior Tool work with Virtual Machines To download the v11.1, Please refer to CodeWarrior for MCUs (Eclipse IDE) v11.1 Best Regards, Luis Re: M&P Multilink As an option you could ask them in their support forum if they have it  PEmicro Support Home Best Regards Re: M&P Multilink Sorry about my other post. I replied to the wrong post (one that I should have closed as solved). You will notice that I have been using CW under a VM for "Many years" and although you can't guarantee it, I know that it works. all I need is the Windows device driver for the Multilink. I think it's somewhere on the P&E website, but I can't find it. So far I have CW running with no problems under windows 11, running in the Parallels VM, loaded in OSX Tahoe.
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S32K3 ADC Optimize DMA Streaming Hello, When the adc group has only one channel and the Adc Enable Optimize DMA Streaming Groups configuration item is checked, a hard fault occurs when the Adc_Ipw_SetupTcdSingleAdcChannelMajorLink function is executed. In the case of a single channel, if the Adc Group Without Interrupts configuration item is checked and ACCESS_MODE_STREAMING, Select Adc Streaming Dma Channel is enabled. Otherwise, the number of the dma channel in the configuration file is 255, which is reasonable here. But what I don't understand is why when ADC_ENABLE_GROUP_STREAMING_RESULTS_RORDER or ADC_OPTIMIZE_DMA_STREAMING_GROUPS is STD_ON, instead of STD_ON==GroupPtr ->AdcWithoutInterrupt, the Adc_Ipw_SetupTcdSingleAdcChannelMajorLink function will be called. This seems unreasonable, and also because the call to this function leads to hard fault. Jason22_0-1785831767968.png BR, Jason Re: S32K3 ADC Optimize DMA Streaming Hi@Jason22 Please do not use your QQ email account next time; please use your company email account instead. I tested this, but I didn't find any problems. I have attached my test project and test result for your reference. Also, i check your code and i found some error in your code. 1.clock init is wrong, your code can't not run successfully, Senlent_0-1785915417329.png 2."adc_group0_val" should be attribute to "no-cacheable area" also: The usage instructions for Optimize DMA streaming groups are clearly explained in the user manual. RTD_ADC_UM.pdf Senlent_0-1785915908665.png Re: S32K3 ADC Optimize DMA Streaming Hi@Senlent The optimization level of my project is -O0, and I ran your project (also with -O0). I found that in Adc_Ipw_SetupTcdSingleAdcChannelMajorLink -> ...... -> Dma_Ip_ConvertLogicChToHwCh, the LogicCh value is still 255. 1.png In your screenshot, was Dma_Ip_ConvertLogicChToHwCh called as a result of Adc_Ipw_SetupTcdSingleAdcChannelMajorLink? Mcl_Init also calls Dma_Ip_ConvertLogicChToHwCh, and in that case LogicCh is 0, which seems consistent with your screenshot. I ran a test in your project. When Adc_Ipw_SetupTcdSingleAdcChannelMajorLink indirectly calls Dma_Ip_ConvertLogicChToHwCh, I observed that &Dma_Ip_pxInit->ppxLogicChannelConfigArray[LogicCh] is 0x429F28, which matches &Dma_Ip_pxInit->ppxLogicChannelConfigArray[255]. 2.png I then modified the value at address 0x429F28 to 0x1FFFFFF0, and executed the code at line 348. 3.png A hard fault occurred, and the BFAR value was 0x1FFFFFF6, as expected. 4.png This confirms that the out‑of‑bounds access does exist. Whether a hard fault occurs depends on the value at Dma_Ip_pxInit->ppxLogicChannelConfigArray[255]. Re: S32K3 ADC Optimize DMA Streaming Hi@Senlent The picture in the last reply is not clear. I have uploaded the picture again in the form of attachment. I numbered the order of the pictures with numbers. BR, Jason Re: S32K3 ADC Optimize DMA Streaming Hi@Senlent Thank you very much for your reply. I have registered a new account using my company email address, and I will use that account after this thread is closed. I ran your project and found that no hard fault occurred. However, my question still remains. As shown in the screenshot below, the function Adc_Ipw_SetupTcdSingleAdcChannelMajorLink configures the DMA_IP_CH_SET_MAJORLOOP_LOGIC_LINK_CH parameter for the DMA channel. When Dma_Ip_ConvertLogicChToHwCh is called, the LogicCh value is 255. Dma_Ip_pxInit->ppxLogicChannelConfigArray points to the Dma_Ip_paxLogicChannelConfigArrayPB array, which has a size of 2. Accessing Dma_Ip_pxInit->ppxLogicChannelConfigArray[255] should be an out‑of‑bounds access. Although no hard fault occurred, I believe this is not reasonable. Jason07_0-1785979871220.png Jason07_1-1785979890128.png Jason07_2-1785979907208.png This out‑of‑bounds access is caused by calling Adc_Ipw_SetupTcdSingleAdcChannelMajorLink, which is another question I have. I have reviewed the relevant content in RTD_ADC_UM.pdf and also checked the driver code. For Optimize DMA Streaming Groups (single channel), the data is transferred directly from the CDR to the user buffer, unlike the multi‑channel case where data is first moved from the CDR to the DmaIntermediateBuffer and then from there to the user buffer. Optimize DMA Streaming Groups (single channel) does not use a Streaming DMA channel. In the configuration file, the values of AdcIpwConfigPtr->Mapping.AdcCountingDmaChanLogicId array are indeed ADC_IPW_INVALID_DMA_CHANNEL_ID (255). Jason07_3-1785980010767.png I do not understand why Adc_Ipw_SetupTcdSingleAdcChannelMajorLink still needs to be called. The function that really should call this is Without Interrupt Group (single channel), but when ADC_ENABLE_GROUP_STREAMING_RESULTS_RORDER or ADC_OPTIMIZE_DMA_STREAMING_GROUPS is STD_ON, instead of STD_ON == GroupPtr ->AdcWithoutInterrupt, the Adc_Ipw_SetupTcdSingleAdcChannelMajorLink function is called. Jason07_4-1785980037684.png I have found the issue in my project: when I uncheck "Data sections", the hard fault no longer occurs. However, I do not think this is the key point of the problem. Jason07_5-1785980062079.png BR, Jason Re: S32K3 ADC Optimize DMA Streaming Hi@Jason07 @Jason22 Please set the optimization build option to -O0 . This is the result I observed during single-step debugging. Senlent_1-1786003373031.png This is likely because the build optimization (-Os) prevents the debugger from accurately mapping source code variables. Re: S32K3 ADC Optimize DMA Streaming Hi@Senlent Yes, I used your project without any modifications. In your video, the Dma_Ip_ConvertLogicChToHwCh function is called indirectly by Mcl_Init, which is not the intended behavior. The intended behavior is for Adc_Ipw_SetupTcdSingleAdcChannelMajorLink to indirectly call Dma_Ip_ConvertLogicChToHwCh. My video demonstrates this: while running Mcl_Init, I skipped all breakpoints, and after Mcl_Init completed, I re‑enabled the breakpoints. At that point, Dma_Ip_ConvertLogicChToHwCh was entered again, and LogicCh was 255. BR, Jason Re: S32K3 ADC Optimize DMA Streaming Hi@Jason22 These are my test results. If you are using the project I provided and the optimization level is set to -O0, then our observations should be the same. I don't think there's anything wrong here. If the boundary is exceeded, it should definitely enter a hard fault, but the test results didn't, which can only mean that it's due to the compilation optimization level. There's no need to continue analyzing under an error condition. Re: S32K3 ADC Optimize DMA Streaming Hi@Senlent I'm glad you can see that LogicCh is 255. In your project, it does run correctly, but this is an out‑of‑bounds access, right? Regarding your statement: "If the boundary is exceeded, it should definitely enter a hard fault" – I don't fully agree with that. In C language, there is no runtime boundary checking like in C++. For a pointer array, whether a hard fault occurs depends on the value obtained from the out‑of‑bounds access. Consider a pointer array: uint32* pArr[2] = {0x20400000, 0x20400004}. Suppose the address of pArr is 0x204300A0, then the value of pArr[2] is the value is stored at address 0x204300A8. If 0x204300A8 contains 0x20400008, then *pArr[2] (an out‑of‑bounds access that ultimately reads the value at address 0x20400008) will not cause a hard fault. However, if 0x204300A8 contains 0x1FFFFFF0, then *pArr[2] (which ultimately reads from 0x1FFFFFF0) will cause a hard fault. Both are out‑of‑bounds accesses, but whether a hard fault occurs is a matter of probability. To be precise, the hard fault is not directly caused by the out‑of‑bounds access itself, but rather because the out‑of‑bounds access to the pointer array got an invalid pointer, and accessing that invalid pointer triggers the hard fault. This is exactly why, in your project, accessing Dma_Ip_pxInit->ppxLogicChannelConfigArray[255]->LogicChId.HwChId does not cause a hard fault, but in my project, it does. BR, Jason Re: S32K3 ADC Optimize DMA Streaming Hi@Jason22 I will send you the design team's feedback. Usually, if it's a bug with significant impact, they will release it in a new version and include it in the release notes.  Re: S32K3 ADC Optimize DMA Streaming Hi@Senlent Thank you very much for reporting this issue to your design team. If there is a final result, where should I check for it? If there is indeed an error, will it be published in a document similar to SW32K3_S32M27x_RTD_R23-11_7.0.0_D2511_ReleaseNotes.pdf? BR, Jason Re: S32K3 ADC Optimize DMA Streaming Hi@Senlent Sorry. Step4 is Click the ‘Step Over’ button. BR, Jason Re: S32K3 ADC Optimize DMA Streaming Hi@Senlent I'm not sure if my operation was correct – I tried debugging with your ELF file but it didn't work. 1.png Could you please perform the same steps as shown in my video? I believe you will be able to reproduce the issue. Here are the steps: Set a breakpoint at the line Mcl_Init(NULL_PTR);. Run the program until it hits the breakpoint at Mcl_Init(NULL_PTR);. Disable all breakpoints (Click the ‘skip all breakpoints’ button). Step over Mcl_Init(NULL_PTR);(Click the ‘Step All’ button) Re‑enable breakpoints(Click the ‘skip all breakpoints’ button) and Click the ‘resume’ button. You will see that Dma_Ip_ConvertLogicChToHwCh is entered again, and LogicCh is 255. BR, Jason Re: S32K3 ADC Optimize DMA Streaming Hi@Jason22 I can forward this issue to the design team for confirmation. Since I wasn't the one who designed the RTD driver, I won't delve into why they designed it this way unless users encounter problems. This feedback process might be lengthy, but I will relay the findings to the relevant design team. Re: S32K3 ADC Optimize DMA Streaming Hi@Jason22 I might still not understand your question. I'd like to ask if this project is running as expected? If it is, is there any problem? I can see LogicCh is showing 255, but the program is running normally. Is there anything wrong with this?
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GUI Builder 2.0生成图片代码bug lqdjdy_0-1785631623960.png lqdjdy_1-1785631779772.png lqdjdy_2-1785631867575.png 生成的宏名带空格 Re: GUI Builder 2.0生成图片代码bug Hello @lqdjdy , 感谢你的帖子。试试看把图片的名字从face-id改成face_id能解决吗? BR Celeste Re: GUI Builder 2.0生成图片代码bug 是的,图片名称不能带中横线 Re: GUI Builder 2.0生成图片代码bug 感谢您的确认。我会向 SW 团队提出建议,在图片名称包含异常字符时弹出异常提示。
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To simulate full load condition on the imx95lpddr5 evk How to simulate the full-load operating condition on the i.MX95 LPDDR5 EVK board. Is there any image available or pre-compiled application for this? I am using linux multimedia image. Re: To simulate full load condition on the imx95lpddr5 evk Hello, You can use this application note as reference: https://www.nxp.com/docs/en/application-note/AN14449.pdf There are different use case scenarios to reach high CPU load testing. I suggest you take a look in: CA55 CoreMark eIQ Benchmark (GPU) eIQ Benchmark (NPU) Best regards. 
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Support for mobile SDRAM (1V8) on RT1171CVM8B We are investigating the use of RT1171CVM8B on a new product. Does this i.MX RT family member support mobile (low power, 1.8V) SDRAM? It is not immediately clear from the datasheet, reference manual and available application notes and schematics that it does; it is inferred by the port drivers being specified for both 1V8 and 3V3 (NVCC_EMC1,2). It is also inferred from similar questions and answers in the affirmative for the i.MX RT1060 and RT1050. I would like to avoid a gotcha where some obscure part of the EMC or SDRAM interface fails with 1V8 parts;  Otherwise, why is it not clearly listed in the datasheet!? Kind regards, George Tzanatos. Re: Support for mobile SDRAM (1V8) on RT1171CVM8B Dear @georgetzanatos , The RT1171 does support Mobile SDRAM (low-power 1.8 V SDRAM). We agree that the current documentation does not state this explicitly. In the datasheet and reference manual, the memory protocol support and I/O voltage modes are described separately rather than being combined into a single "Mobile SDRAM support" statement. I understand your concern. Please feel free to use Mobile SDRAM on the RT1171. The key requirement is to configure the relevant NVCC_EMC1/2 power domains for 1.8V operation to match the SDRAM I/O voltage level.   Best Regards, Shelly
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MC9S08QG8 COMPILER, how do i get the c compiler for this chip well, i have a product developed with a MC9S08QG8 chip. i need to make some c code changes. i am using windows11. What software product do i use to generate the debugger for the chip. I am using a Wiztronics interface board from the pc usb port to the chip in my product. i have tried 8 different software packages, and none of them have the final debugger working. What softwage package do u suggest to use for debugging.  I am lost in ur devlopment center . Re: MC9S08QG8 COMPILER, how do i get the c compiler for this chip Hello The CodeWarrior tool version 11.1, is supported in windows 11, this tool supports different connections [P&E USB Multilink Universal / USB Multilink, P&E Cyclone, Open Source BDM, P&E Full chip simulation] You can download the tool from this link: CodeWarrior® for MCUs (Eclipse IDE) v11.1 I look for the MC9S08QG8 device and is available in this version. Best Regards, Luis
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Request for NXP V2X Evaluation Board and Design Files Dear NXP Team, We are evaluating V2X communication solutions for an automotive application supporting V2V, V2I and V2P safety messages. We are interested in NXP’s RoadLINK/SAF5400-based V2X solution and the OrangeBox platform. Kindly provide the following information: Recommended NXP V2X evaluation board or reference platform Evaluation-board ordering part number SAF5400 availability and lifecycle status Reference schematic and hardware design files Bill of materials and PCB layout guidelines RF matching and antenna reference design Hardware user manual and software development kit BSP, drivers and example applications Functional-safety documentation, including ASIL-B support details Security-device recommendations for V2X message signing and verification NDA procedure for accessing controlled technical documents Our intended application is an automotive V2X communication unit operating in the 5.9 GHz band. Please also confirm whether NXP currently offers a solution supporting DSRC/IEEE 802.11p, C-V2X PC5, or both. Kindly share the applicable product documents, commercial contact details and procurement process. Best regards, Renjith Thomas Senior Design Engineer - HW Get My Solutions +91 8015237416 Re: Request for NXP V2X Evaluation Board and Design Files Hello, Hope you’re doing well. This is our DSRC Safety Modem product catalog for automotive V2X applications: DSRC Safety Modem. You can also find our recommended Products for V2X Communications here. The RoadLINK SAF5400 is an automotive-qualified single chip DSRC modem for V2X applications, compliant with IEEE 802.11p, IEEE 1609.4, ETSI EN 302663, ETSI EN 302571, and ARIB T-109M. I'm sorry for the inconveniences this may cause, but, unfortunately, information about the SAF5400 and other V2X Automotive Products is protected under a Non-Disclosure Agreement. To obtain information about these products, could you please contact your Local Distributor from the Distributor Network so they can not only help you with the NDA process but also provide you the information you might need of those products? Best regards, Ana Sofia.
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S32K312 HSE Secure Boot: Can pInstAuthTag Point to a Signature Stored in the UTEST DCF Record Area? Hello NXP Support Team, We are implementing HSE-based Secure Boot with SMR on the S32K312 and would like to confirm whether an SMR signature can be permanently stored in the UTEST DCF record area. Our current implementation is as follows: We store a 512-byte RSA-4096 signature in UTEST, starting at address: 0x1B001A00U The occupied address range is: 0x1B001A00 to 0x1B001BFF This region belongs to the UTEST DCF record area. Our project does not require any DCF configuration in this area. Therefore, we are currently considering using the unused DCF record space to store permanent security data, including the public key and the SMR signature. Since the software image and its signature are fixed in our use case, the signature is not expected to change during the product lifetime. In the SMR Entry, we configure the signature reference as follows: smrEntry.pInstAuthTag[0] = 0x1B001A00U; smrEntry.pInstAuthTag[1] = 0U; Our expectation is that, during subsequent Secure Boot verification, HSE will read the 512-byte signature directly from the UTEST address specified by pInstAuthTag[0]. When installing the SMR Entry through HSE_SRV_ID_SMR_ENTRY_INSTALL, we initially configured the installation service authentication tag to reference the same UTEST address: pSmrEntryInstall->pAuthTag[0] = 0x1B000A00U; However, the SMR installation service returned HSE_SRV_RSP_INVALID_PARAM, apparently because the UTEST address was rejected as an invalid input address for the service. As a workaround, before calling the SMR installation service, we copy the 512-byte signature from UTEST into a shared RAM buffer: UTEST 0x1B000A00 | | Copy 512 bytes v Shared RAM buffer We then configure the installation request as follows: pSmrEntryInstall->pAuthTag[0] = PTR_TO_HOST_ADDR(signatureRamBuffer);   pSmrEntryInstall->authTagLength[0] = 512U; The SMR Entry itself still contains: smrEntry.pInstAuthTag[0] = 0x1B000A00U; With this configuration, HSE_SRV_ID_SMR_ENTRY_INSTALL returns success and the SMR Entry is installed successfully. Could you please clarify the following questions? Is 0x1B001A00U a valid address for hseSmrEntry_t.pInstAuthTag[0] on the S32K312? During a subsequent Secure Boot, can HSE_B directly access the UTEST DCF record area and read the signature referenced by pInstAuthTag[0]? Does a successful HSE_SRV_ID_SMR_ENTRY_INSTALL response confirm that the persistent pInstAuthTag[0] address is valid for later boot-time SMR verification, or does the installation service only verify the signature supplied through hseSmrEntryInstallSrv_t.pAuthTag[0]? Is there a difference between the memory regions accepted for: hseSmrEntryInstallSrv_t.pAuthTag[0] and: hseSmrEntry_t.pInstAuthTag[0] In our test, the UTEST address is rejected when used directly as pAuthTag[0], but the SMR installation succeeds when the same signature is copied to RAM while pInstAuthTag[0] still points to UTEST. Could this configuration pass SMR installation but fail during the next reset or Secure Boot because HSE cannot access the UTEST address at boot time? Is the unused UTEST DCF record area allowed to store customer application data such as a public key or an SMR signature when no DCF records are required by the project? Could using this DCF record area cause any conflict with HSE firmware, ROM boot code, future DCF processing, lifecycle transitions, debug configuration, or device configuration scanning? Are there any alignment, record-format, ECC, programming, locking, or access restrictions for storing a raw 512-byte signature in this UTEST area? If UTEST is not supported for pInstAuthTag[0], should the persistent SMR signature always be stored in normal application Code Flash or Data Flash? The main point we would like to confirm is whether the following configuration is officially supported and safe for production: /* Persistent signature location used during Secure Boot / smrEntry.pInstAuthTag[0] = 0x1B000A00U;   / Temporary RAM copy used only during SMR installation */ pSmrEntryInstall->pAuthTag[0] = PTR_TO_HOST_ADDR(signatureRamBuffer);   pSmrEntryInstall->authTagLength[0] = 512U; MCU: S32K312 HSE type: HSE_B Signature algorithm: RSASSA-PSS with RSA-4096 Signature length: 512 bytes Persistent signature address: 0x1B001A00U Thank you. Re: S32K312 HSE Secure Boot: Can pInstAuthTag Point to a Signature Stored in the UTEST DCF Record Ar sorry the Signature location is not 0x1B000A00U. it is 0x1B001A00U. Re: S32K312 HSE Secure Boot: Can pInstAuthTag Point to a Signature Stored in the UTEST DCF Record Ar Hi @Yiming2  I tested it on my board because it is not explicitly mentioned in the documentation if UTEST can be used or not. And I got similar results. If pAuthTag = pInstAuthTag = 0x1B001A00, I got HSE_ SRV_ RSP_ INVALID_ ADDR response. Then I placed pAuthTag into RAM memory while pInstAuthTag was pointing still to UTEST and this works. Once secure boot is enabled by BOOT_SEQ bit, secure boot is successful, application is working. HSE is able to read the signature in UTEST DCF area. Based on the test results, HSE firmware obviously checks if address pAuthTag falls within RAM or code/data flash memory while pInstAuthTag in UTEST is accepted. It’s not documented but it works. But if you do not plan to update the signature, an option is to keep HSE_SMR_CFG_FLAG_INSTALL_AUTH zero, so internal verification scheme (internal hash) would be used for verification. Your signature would be used only for installation and pInstAuthTag would be ignored. In my opinion, this setup makes more sense if you do not plan to update the image. Also the verification would be much faster (hash vs. RSA algorithm). This is probably the best way to keep it simple and to get better performance. If HSE_SMR_CFG_FLAG_INSTALL_AUTH is set and pInstAuthTag is used, this targets mainly a use-case when you want to easily update an application: application and authentication tag is updated and you do not need to modify or reinstall that SMR. DCF is scanned up to stop record (all 0xFF’s), the rest is ignored. Normally the DCF area is not supposed to be used for user data but I can’t see a problem here. The only restriction for UTEST is that it is OTP area. And the same ECC limitations apply (like for code or data flash) – once an aligned double word is programmed, you should not program the same double word again because it would cause ECC error. Regards, Lukas
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How use adjust SOI -EOI with use MC33 PT2000 IC just as topic, we need the help which can esstablished whole process , which use PT2000 to apply fule injection SOI -EOI measurement  H-Bridge Driver Small Engine Driver Solenoid Controller Re: How use adjust SOI -EOI with use MC33 PT2000 IC appreciated! Re: How use adjust SOI -EOI with use MC33 PT2000 IC Dear Kaijinbin,  there is an PT2000 end of injection detection application note available to download from the PT2000 product page, with a valid NDA.  JozefKozon_0-1786079976443.png If you don't have an NDA yet and you would like to sign one, please create a new ticket here and our representative for NDA matters will help you with the process.  Additionally please download the PT2000SWUG and PT2000-IDEUG from the FRDMPKPT2000EVM product page. You can download the PT2000 Developer Studio IDE and Software Files for Peak and Hold and DCDC software from the same page. You can then test the software example on the FRDMPKPT2000EVM Evaluation Board.  JozefKozon_1-1786080423866.png With Best Regards, Jozef
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Detail about S32K338 Good morning, I need to know if the S32K388 microcontroller has three independent cores, like the K324 (which has two), and if two of these cores can also be used in Lockstep. If I want one single core + one Lockstep core, should I use the K358? Thanks Re: Detail about S32K338 Hello @gianpiero_lenta , Lockstep operation is not a software-configurable feature that can be enabled between two independent cores. Instead, Lockstep is a dedicated hardware configuration implemented in specific S32K3 derivatives. Therefore, if your application requires one independent Cortex-M7 core together with a Lockstep Cortex-M7 pair, I recommend using the S32K358, which is designed with this hardware configuration. Best regards, Pavel
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IMX8 ISP operating only on ROI Hi. We are facing some problems about the ISP service in our IMX8 products. We should be able to make ISP work only on a determined ROI of the picture coming from MIPI. In fact, now we can only use ISP on the whole image coming from ISP. As an example, in our case we have an image of size 1120x1376, but the last 16 rows are embedded data that we cannot send in another VC. The ISP should work on the picture (1120x1360) and not on the embedded data (that are always in the bottom of the picture). Is it possible to do this? Thanks in advance! Have a nice day. Federico Rachelli, Datalogic S.r.l. Re: IMX8 ISP operating only on ROI Hello @federico_rachelli  Hope you are doing very well. We have not an example of this, but it makes me think you can do it at driver level. For example, the ACQ module uses the bounds_width and bounds_height parameters to understand the raw MIPI payload dimensions, and then uses top, left, width, and height to extract the effective Region of Interest (ROI). You can see that information in the i.MX 8M Plus Camera and Display Guide. To discard the 16 rows of embedded data at the bottom of your 1120x1376 frame, you need to set the .size property in your sensor's ISP driver configuration: .size = { .bounds_width = 1120, .bounds_height = 1376, /* Total MIPI payload including embedded data */ .top = 0, .left = 0, .width = 1120, .height = 1360, /* Effective image height (1376 - 16) */ }, Take a look to the chapter 4.1.2 Sensor size configuration in driver of the document mentioned above. Best regards, Salas.
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SWO Data Trace functionallity (on MCXA156) Hello NXP Community, I have been experimenting with the Debug functionalities of the MCXA156 Controller and its respective development board. My setup: (FRDM-MCXA156) as well as MCXA156 in a custom board. MCUXpresso IDE v25.6 [Build 136] [2025-06-27] MCU Link pro Debugger So far with various examples from the NXP Expresso SDK I was able to cover most of debugging needs. (Breakpoints, Datawatch points, ITM printf redirect, Interrupt tracing etc.) Somehow I am stuck with usage of Data Watch Trace/Stream over SWO. I am at a point where I think I have misunderstood the capabilities of the MXCA156 debugging feature. To my understanding the MCXA156 supports ITM and DWT. With this it should be possible to add read/write data comperators and stream/trace out the appropriate data over the SWO pin. With my setup it seems I cant get to work the "SWO Data" window to work even if all other tracing feature seems to work fine. I am on the right track with my setup or does the MCUXpresso IDE simply not supporting my use-case yet? Best regards Alex Re: SWO Data Trace functionallity (on MCXA156) Hello @AlexRu  To use SWO, you can follow the provided step guide. Hardware Requirements: Ensure that the chip’s SWO pin is connected to the debugger’s SWO interface. (This is FRDM-MCXN947 board) Alice_Yang_0-1764234995466.png Software Configuration: When creating a new project, select “Redirect printf/scanf to ITM” to redirect printf/scanf output to ITM. Alice_Yang_1-1764235038209.png 2. Configure the Trace Clock: Alice_Yang_2-1764235054451.png CLOCK_AttachClk(kTRACE_DIV_to_TRACE); /*! Switch TRACE to TRACE_DIV */ /*! Set up dividers */ CLOCK_SetClkDiv(kCLOCK_DivTraceClk, 3U); /*! Set TRACECLKDIV divider to value 3 */ 3. Configure ITM Console View in MCUXpresso IDE: Open SWO ITM Console. Configure the corresponding Core Clock and Trace Clock in both the IDE settings and your code    . Alice_Yang_4-1764235140283.png Alice_Yang_5-1764235162015.png Alice_Yang_6-1764235196129.png Alice_Yang_7-1764235214710.png Alice_Yang_8-1764235219324.png 4. View the Output Results. Alice_Yang_9-1764235228270.png For details on SWO and DWT usage, please refer to MCUXpresso_IDE_25.06_Instruction_Trace_Guide.pdf. You can find this guide under MCUXpresso IDE install path.  BR Alice   Re: SWO Data Trace functionallity (on MCXA156) Hi Alice, thank you very much for your detailed visualisations on how to setup the SWO Tracing. In my case I already verified the electrical connection of the SWO pin (MXCA-156 PCB) to my MCU-Link Pro Debug Probe. The PDF you mentioned has indeed more detailed information and extends my knowledge. Nevertheless it does not really explain/disprove my assumutions of DWT usage. In my setup I already see data from Interrupt returns and Interrupt entry points in the "SWO Interrupts" windows: (this is live data from my SW! Meaningfull data and correct timing information.) AlexRu_0-1764332623019.png With this information I verfied that my electrical connection via SWO pin is working, trace clocks are enabled and frequency is as expected in my SWO Trace Config. What I am missing (or maybe there is a misunderstanding on my side?) is the function to trace Data via a Data Watch comparator (DWT) to the SWO trace pin in window "SWO Data". After enabeling the "play" button I dont receive any trace information:  AlexRu_1-1764333027216.png I even veriefied that with my config of MXCA156 the data watchpoints are limited to 2 comparators, so the IDE seems to be able to set them and warns about too many Data Watch points set (I did it intentionally to check the plausibility): AlexRu_2-1764333135738.png So my question is: Does the IDE support this method of debugging or is there a misunderstanding on my side and the DWT does not provide this kind of Data tracing capabilities at all? Re: SWO Data Trace functionallity (on MCXA156) Hello @AlexRu  Thanks for your reply. Could you please let me know which data you want to use DWT to watch? Also, please share a project that can reproduce the issue and provide a video showing all the steps you took. I will use this information to reproduce and check the issue on my side. Thank you! BR Alice Re: SWO Data Trace functionallity (on MCXA156) Hello @Alice_Yang , I did prepare a minimalistic Project based on the SDK Example (LED Blinky) for the FRDM-MCXN236 Demonstration Board. (demo_apps -> LED_BLINKY_PERIPHERAL) The MCXN236 Board setup seems to show the same effect as the MCXA156 Board I used before. I just wanted to confirm this behaviour on another Board. Pin config set P0_2 -> Output SWO (Default in this example) Enabled the TRACECLK and TRACECLKDIV (1) as this example uses BOARD_BootClockFRO12M() Added following code to see some action on glocal ram variables: volatile uint32_t debug_cnt = 0; void SysTick_Handler(void) { /* Toggle pin connected to LED */ GPIO_PortToggle(BOARD_LED_GPIO, 1u << BOARD_LED_GPIO_PIN); debug_cnt++; //<- added for demonstration purpose }  Attachments: Zip with demo project, video of my debug session. You can see that "SWO Data" does not show any tracing data. Global variables window shows the increment of debug_cnt in SysTick_Handler cycle of ~1s. Also "SWO Interrupts" shows the entry and exit of SysTick_Handler() reliably so the electrical connection of SWO trace seems to work correctly. Let me know if I can provide more info to narrow down this issue. I would also be happy if you could confirm whether my expectation of tracing a global/static RAM variable with DWT is possible. Or I have a misunderstanding. Re: SWO Data Trace functionallity (on MCXA156) Hi Alice, thank you for your effort. So it seems that MCUXpresso does not support the "data trace" debugging currently. Is it possible to request this for future releases? From my outsider perspective it seems that there is not much missing to make it work. SWO Interrupt seems to work just finde and extends to advanced debugging functionalities. SWO Data tracing whould further extend the possibilities for Debugging in NXPs Xpresso Toolchain. Best regards Alex Re: SWO Data Trace functionallity (on MCXA156) Hello @AlexRu  I tested on my side. This cannot output the variable’s value in real time. It can only check the variable’s value when debugging is paused. Alice_Yang_0-1765449677747.png BR Alice Re: SWO Data Trace functionallity (on MCXA156) Hello @AlexRu  Thank you for your reply. I will forward this request to the MCUXpresso development team and keep you updated on any progress. Thank you.   BR Alice Re: SWO Data Trace functionallity (on MCXA156) Hello @Alice_Yang @AlexRu  I am currently working with the FRDM-MCXA156 development board and have been facing an issue with SWO (Serial Wire Output) while debugging. Although the application debugs successfully, I am unable to receive any data in the SWO Trace windows, including: SWO Data SWO Profile SWO Interrupt Trace ITM Console  To troubleshoot the issue, I have already verified the following: The SWO pin has been correctly configured using Config Tools. The TRACE clock is enabled and configured to 96 MHz, matching the MCU core clock (MCXA156 runs at 96 MHz). The project is being debugged using LinkServer with the on-board MCU-Link probe. Despite these configurations, all the SWO trace windows remain empty during debugging. For reference, I have attached screenshots of the SWO Trace Configuration, SWO Data, SWO Profile, and SWO Interrupt Trace windows. I would greatly appreciate any guidance or suggestions on what might be causing this issue or if there are any additional configuration steps required to enable SWO trace on the FRDM-MCXA156. Thank you for your time and assistance.
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RTD update issue - MBDT In the S32 Design Studio version 3.6.1, wanted to update the RTD version 7.0.0 but i could only update it to 5.0.0, its showing error when i try updating RTD version 6.0.0 and further.  Screenshot 2026-08-06 143602.png Eclipse IDE Usage and Settings SDKs Re: RTD update issue - MBDT Screenshot 2026-08-07 101727.png i have installed the IDE 3.6.10 version, and tried to download the rtd version 7.0.1 but i couldnt, system network is connected properly, and it shows network issues only with this version and when i was working with the previous version 3.6.0 i didnt face any network issues. whenever i am opening the S32 IDE application the message box attached, pops up. If this is the case with changing network preferences, can you tell wat are the things to enable and disable in the settings? Screenshot 2026-08-07 095218.png Screenshot 2026-08-07 102413.png and the RTD gets installed, and when i am trying to check with example project (DIO S32k344) it shows the above error as attached,  in creating a new project i could not find any SDK options.  Screenshot 2026-08-07 102457.png Re: RTD update issue - MBDT Hi @Rathidevi  First, we recommend updating your S32DS installation to version 3.6.10. There is no need to install it as a separate instance, as it can be installed as an update to your existing S32DS installation. Detailed instructions are available in the S32 Design Studio 3.6.10 RFP Installation Guide, which can be found on the same download page as the S32DS installer. This update is recommended because RTD 7.0.1 was developed and validated using S32DS 3.6.4. To ensure compatibility and proper functionality, the IDE version should be the same as or newer than the version used for validation. Additionally, this requirement is noted in the Missing Requirements of the shared image. Regarding the RTD 7.0.1 installation, we recommend first uninstalling the currently installed RTD version and then installing RTD 7.0.1. This helps avoid potential conflicts between different RTD versions. BR, VaneB Re: RTD update issue - MBDT Hi @Rathidevi  It seems that the toolchain required by the RTD is missing from your installation. Please install NXP GCC for Arm Release version 10.2 build 1728. This should fix the problems with the examples and should also make RTD 7.0.1 available as an SDK option when creating a new project, as long as GCC 10.2 is selected as the project's toolchain.
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CodeWarror Does anyone know where I can download a copy of CodeWarrior for 8-bit processors that will run under Linux (Ubuntu)? A general enquiry showed that C/W does run under linux, but all of the links are for windows. Re: CodeWarror Hello, Sorry for the inconveniences, the available version of CodeWarrior for 8-bit processors [CodeWarrior v11.1] is not available for Linux only windows. Best Regards, Luis Re: CodeWarror I know that! I have been using CW for "many years", running under Windows 7 which is running under Dropbox which is running under OSX on my Intel-based MAC. All I want is to do the same thing on my new ARM-based MAC. So far I have installed Dropbox and loaded Windows 11. (earlier versions of Windows are not compatible with the new MACs). I have installed CW 11.1 in Windows and it works. As I said in my original post CW does not recognise the Multilik debug probe because there is no device driver installed. Please refer to my original post for details of what is required 
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Reinstalling the S32DS environment and SDK package has caused previous projects to fail to compile Reinstalling the S32DS environment and SDK package has caused previous projects to fail to compile. In the past, my project used S32DS V2.2 and SDK RTM 2.0.0. Now, after reinstallation, I am using S32DS.ARM.2018.R1 and have also installed SDK RTM 2.0.0. But now I can't compile the project. It seems that it can't recognize the project itself. You can see the details in the picture. Re: Reinstalling the S32DS environment and SDK package has caused previous projects to fail to compi Hi @yangcao1234  Please note that S32K1 SDK RTM 2.0.0 was released specifically for S32DS for ARM 2018.R1 Update 6. It was not intended to be used with S32DS for ARM 2.2, and compatibility with that version is not guaranteed. BR, VaneB
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SL3S1206FUD2/HA Request for Good Die identification documentation / Wafer Map Dear Supplier, We would like to confirm whether you have provided any documentation or markings that distinguish “Good Die” from “NG Die” on the wafer. Specifically, we are looking for: A wafer map (indicating which die passed/failed testing), A test result report, or Physical markings on the wafer surface (e.g., ink dots, laser marks) that clearly identify usable die. After inspecting the wafer under our microscope, we could not find any visible physical markings. This raises concerns that we may not be able to reliably differentiate good die from defective die. Could you please help check whether such information was included with the shipment, or assist us in obtaining these materials from the manufacturer? We need this data for our subsequent processing steps. Thank you for your kind assistance. We look forward to your reply.
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Concern about Guiguider License Compliance Dear NXP Semiconductors, I am writing to report a potential violation of the license agreement for your Guider software. As we understand, the license for your Guider software explicitly prohibits its commercial use in the development of products based on non-NXP series chips. However, a major multinational corporation is currently using this software in the development of commercial products based on Rockchip series main control chips, which appears to be a clear breach of your license terms. I would like to ask: Does NXP plan to take any enforcement actions to protect its intellectual property rights in this matter? Additionally, if I were to file a formal complaint regarding this violation, what specific evidence would you require to initiate an investigation? I look forward to your response. 回复: Concern about Guiguider License Compliance Guiguider is being used in violation of its license. Your company's Guider software license explicitly prohibits its use in commercial development of non-NXP series chips. A large multinational corporation has violated this license by applying the software to commercial products using Rockchip's main control chips. Will your company take legal action? If I wish to file a complaint, what evidence should I provide? Re: Concern about Guiguider License Compliance Thank you for raising this concern. GUI Guider is provided subject to license terms that govern its permitted use, including limitations regarding supported hardware platforms. NXP expects users of its software tools to comply with the applicable license terms.  We are not aware of the specific circumstances referenced in your post and therefore cannot comment on any particular company, product, or alleged activity. If you have specific information regarding potential misuse of GUI Guider, please provide additional details through the appropriate direct NXP channels (rather than via community postings) so that the information can be reviewed. Examples of helpful information may include the identity of the organization involved, details regarding the product or project, or other supporting information. We appreciate your interest in NXP products and software tools.
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Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Hello NXP Support Team, We are evaluating object detection on the FRDM i.MX95 platform using the Neutron SDK v3.1.3 and are unable to generate an NPU-compatible model. The Neutron converter successfully loads the model, but reports that 0 operators are mapped to the Neutron NPU. Environment Target Board: FRDM i.MX95 Neutron SDK: 3.1.3 Ultralytics: Tested with both YOLO11 and YOLOv8 eIQ Toolkit: Used for ONNX → TFLite conversion Model: Custom single-class peg detector Training Command $ yolo detect train \ model=yolov11n.pt \ data=/visual_inspect_yolo/dataset/dataset.yaml \ imgsz=640 \ epochs=100 \ batch=16 \ project=models \ name=peg_detector_v8 Export Command $ yolo export \ model=models/peg_detector_v84/weights/best.pt \ format=tflite \ int8=True \ data=/visual_inspect_yolo/dataset/dataset.yaml We also tested an alternative workflow: Export PyTorch → ONNX Convert ONNX → INT8 TFLite using the NXP eIQ Toolkit Both workflows produced the same result when compiled with the Neutron SDK.   Neutron Compilation ~/Downloads/eiq-neutron-sdk-linux-3.1.3/bin/neutron-converter \ --target imx95 \ --input best_int8.tflite \ --output my_model_int8_npu.tflite   Converter Output The converter reports: Operators after import: 341 Operators after optimization: 367 Operators converted: 0 Operator conversion ratio: 0 / 367 Number of Neutron graphs: 0 Warnings: WARNING: None of the operators from the graph was mapped to Neutron. WARNING: The converted model is the same as the input model because no operators were mapped to Neutron. WARNING: Graph has FLOAT operators which are NOT supported! This can result in low conversion ratio. Additional Information We observed the same behavior with: YOLO11 YOLOv8 Direct Ultralytics TFLite export ONNX → eIQ Toolkit → INT8 TFLite All generated TFLite models result in 0 operators being mapped by the Neutron compiler. Questions Are YOLOv8 or YOLO11 object detection models officially supported by the Neutron compiler for the i.MX95? Is there a recommended export pipeline for YOLO models targeting the i.MX95 NPU? Are there any known limitations with the current Neutron SDK (v3.1.3) regarding YOLO detection heads? Does NXP provide a reference YOLOv8/YOLO11 model that successfully compiles for the i.MX95 NPU? Is there any additional compiler option or preprocessing step required to enable operator mapping? We would appreciate any guidance, recommended workflows, or reference models that are known to work with the i.MX95 Neutron NPU. Thank you. Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Thank you for your response. I would like to inquire if there is a standard procedure available for training, exporting, and deploying models on the IMX95 board. As we currently have the ARA2, we are looking to fully utilize its capabilities and customize our models. We have upcoming demos for NXP Tech Days, and your assistance in this matter would be greatly appreciated. Thank you for your help. Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Tried the yolo8m model from eIQ model zoo on imx95 board with LF 2026 Q2 release image. kernel version is 6.18.20 using neutron SDK 3.1.2. it works. xing_lei_0-1783672312304 (1).png     You can try it firstly by: wget https://huggingface.co/EdgeFirst/yolov8-det/resolve/main/imx95/yolov8n-det-int8-smart.imx95.tflite root@imx95evk:/usr/bin/tensorflow-lite-2.19.0/examples# ./benchmark_model --graph=yolov8n-det-int8-smart.imx95.tflite --external_delegate_path=/usr/lib/libneutron_delegate.so more info you can refer the README eiq-model-zoo/tasks/vision/object-detection/yolov8 at main · NXP/eiq-model-zoo What's more, you can attached model and details log of convert/complier. Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Based on the converter log, the first issue to resolve is that the generated TFLite model still contains FLOAT operators:   WARNING: Graph has FLOAT operators which are NOT supported! For i.MX95 Neutron, the input to neutron-converter must be a TFLite model whose operators and quantization format are compatible with the Neutron compiler. In particular, the i.MX95 Neutron flow expects quantized TFLite and symmetric int8 weights. If the model still contains FLOAT operators/tensors after the Ultralytics export or ONNX-to-TFLite conversion, the converter may be unable to create any Neutron-compatible subgraph, which is consistent with the reported result:   Operators converted: 0   Number of Neutron graphs: 0 YOLOv8 has been evaluated on i.MX95 in some flows, but full end-to-end YOLOv8/YOLO11 offload should not be assumed for arbitrary Ultralytics exports. Depending on the exported TFLite graph, only part of the model may be converted to NeutronGraph and unsupported operators will remain on CPU. Therefore, the recommended next step is to inspect/profile the generated TFLite model and confirm: the graph is fully quantized, there are no FLOAT operators, weights are symmetric int8, input/output tensor types are compatible, or converted with the Neutron converter uint8-to-int8 options if applicable, YOLO post-processing such as decode/NMS is kept outside the NPU graph unless the exact operators are confirmed supported by the SDK. Please also ensure that the neutron-converter version and the Neutron runtime/firmware/delegate on the board are from the same compatible SDK/BSP release. As a recommended flow, please try the NXP/eIQ conversion path:   PyTorch -> ONNX with static input shape -> NXP/eIQ quantization with representative calibration data -> quantized TFLite -> neutron-converter --target imx95 If the model has uint8 input/output tensors, please also test:   --convert-inputs-uint8-to-int8   --convert-outputs-uint8-to-int8 If the conversion still reports 0 mapped operators after removing FLOAT operators, please share:   - the complete neutron-converter log with verbose/profiling output if available,   - the TFLite operator list,   - tensor data types and quantization parameters,   - the exact BSP/runtime Neutron delegate/firmware versions on the FRDM i.MX95 board,   - whether the YOLO detection head includes NMS or other post-processing inside the TFLite graph. Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Hi  i am running ubuntu 24.04, but eiq_toolkit is avaialble for only 20.04.03.  how can i use eiqToolkit and Quantization Using eIQ Toolkit Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Recommended End-to-End Workflow Model Training (PC) Train using your preferred framework: Ultralytics YOLOv8 PyTorch TensorFlow ONNX-native workflows For object detection, NXP already provides YOLO reference recipes in the eIQ Model Zoo, including YOLOv8 object detection models. [github.com], [github.com] Example: Shell yolo detect train \ model=yolov8n.pt \ data=dataset.yaml \ imgsz=640 \ epochs=100 ` Export to ONNX NXP generally recommends using ONNX as the interchange format before quantization and deployment. yolo export \ model=best.pt \ format=onnx The Neutron enablement presentations explicitly describe a flow based on: Plain Text PyTorch ↓ ONNX ↓ Quantization ↓ TFLite ↓ Neutron Converter rather than directly targeting deployment from training artifacts. Quantization Using eIQ Toolkit The Neutron workflow documentation recommends using the eIQ Toolkit quantization utilities: python -m onnx2quant \ model.onnx \ -o model_quant.onnx \ -c input:: `` followed by: python -m onnx2tflite \ model_quant.onnx \ -o model_int8.tflite Show more lines This flow is explicitly documented in the i.MX95 Neutron enablement material. Compile for i.MX95 Neutron NPU neutron-converter \ --target imx95 \ --input model_int8.tflite \ --output model_neutron.tflite The Neutron converter creates Neutron-specific graph partitions that can be offloaded to the NPU. Validate Conversion Ratio A successful NPU deployment should report something similar to: Number of operators converted > 0 Number of Neutron graphs > 0 If you see: Operators converted: 0 Number of Neutron graphs: 0 then the model is not being accelerated by the NPU. Your current issue falls into this category. Deploy on FRDM-i.MX95 Run using TensorFlow Lite with the Neutron delegate: ./benchmark_model \ --graph=model_neutron.tflite \ --external_delegate_path=/usr/lib/libneutron_delegate.so `` or ./label_image \ --external_delegate_path=/usr/lib/libneutron_delegate.so The i.MX Machine Learning User Guide identifies the Neutron Delegate as the acceleration mechanism for i.MX95 TensorFlow Lite models. Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU In my test I did not train or export the model myself. I used a pre-generated YOLOv8 model from the eIQ Model Zoo and verified that it runs on the i.MX95 platform. The only command I actually used was: ./benchmark_model \ --graph=yolov8n-det-int8-smart.imx95.tflite \ --external_delegate_path=/usr/lib/libneutron_delegate.so `` with the model: wget https://huggingface.co/EdgeFirst/yolov8-det/resolve/main/imx95/yolov8n-det-int8-smart.imx95.tflite For custom models, the recommended NXP flow is: PyTorch ↓ ONNX (static input shape) ↓ eIQ Toolkit ONNX2Quant ↓ eIQ Toolkit ONNX2TFLite ↓ Quantized TFLite ↓ neutron-converter --target imx95 Since your model reports: Plain Text Operators converted: 0 Number of Neutron graphs: 0 WARNING: Graph has FLOAT operators which are NOT supported! I suspect your generated TFLite graph is structurally different from the eIQ Model Zoo reference model. The first thing I would recommend is comparing the two models for: Input/output tensor type (INT8 vs UINT8) Presence of FLOAT operators Decode/NMS layers inside the graph Operator list reported by Netron / TFLite analyzer Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Can you please tell me how did you convert yolov8m_full_integer_quant.tflite to be able to run on the imx95 NPU?  Step followed and environment setup data(HOST).. would greatly help us. Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Since eIQ Toolkit was validated on Ubuntu 20.04, the safest approach is: Docker Run a Ubuntu 20.04 container on your Ubuntu 24.04 host: docker run -it --name eiq \ ubuntu:20.04 /bin/bash Then install the required dependencies and eIQ Toolkit inside the container. Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Unable to preserve confidence output when converting custom YOLOv8 ONNX model using eIQ Toolkit (onnx2quant) Overview Hi NXP Team, I'm trying to deploy a custom YOLOv8 single-class object detection model on the FRDM i.MX95 using the eIQ Toolkit. The complete conversion pipeline runs successfully, but after onnx2quant, the confidence output becomes all zeros while the bounding box outputs remain valid. Environment - Ubuntu 24.04 - Python 3.10 - eIQ ONNX2TFLite 0.9.0 - ONNX Runtime 1.21.1 - TensorFlow 2.21 - neutron-converter 3.1.3 - Target: FRDM i.MX95 (tflite_runtime 2.19 + Neutron delegate) Conversion Pipeline 1. Train yolo detect train model=yolov8n.pt data=dataset.yaml imgsz=640 epochs=50 2. Export ONNX yolo export model=best.pt format=onnx opset=13 3. Verify ONNX Input : (1,3,640,640) Output: (1,5,8400) ONNX Runtime inference: Confidence Channel Max = 0.773 4. Generate calibration dataset Shape : (1,3,640,640) dtype : float32 Range : 0.0 - 1.0 5. Quantize onnx2quant best.onnx -c "images;calibration/images" -o best_quant.onnx Also tested: onnx2quant best.onnx -u Both produce the same result. 6. Verify Quantized ONNX Output : (1,5,8400) Bounding box channels remain valid. Confidence: Min = 0 Max = 0 Mean = 0 Decoded detections = 0 7. Convert to TFLite onnx2tflite best_quant.onnx -o best.tflite 8. Compile for Neutron neutron-converter --target imx95 --input best.tflite --output best_neutron.tflite Compilation succeeds. Operator conversion: 278 / 325 (85.5%) Investigation Performed Verified: • PyTorch model works • ONNX export works • ONNX Runtime inference works • Calibration dataset is correct • Real and random calibration produce identical results • TFLite reproduces the Quantized ONNX output • Neutron reproduces the TFLite output The issue first appears after: ONNX ↓ onnx2quant ↓ Quantized ONNX (confidence becomes zero) Additional Observation NXP reference model: Input : (1,640,640,3) INT8 Output: (1,84,8400) INT8 My converted model: Input : (1,3,640,640) FLOAT32 Output: (1,5,8400) FLOAT32 Is there a recommended export or quantization workflow for custom YOLOv8 models that preserves the confidence output? Could this be a limitation or bug in onnx2quant for models with a (1,5,8400) output? Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Discussing with the AE team. Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Has end-to-end been evaluated for the Ara240? The datasheet mentions two vector cores that can execute post-processing ops such as sigmoid and NMS. Could the compiler map NMS ops to the vector cores? Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Sorry for the delay. I am trying to reproduce the conversion workflow.  One question for now, why the converted model's data type is FLOAT32? Have you tried to convert to INT8? The Neutron NPU requires the INT8 type as input data. I met the similar error on other models conversion and the root cause is the data type. Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU The confidence output is lost due to a fundamental limitation of full INT8 quantization ( inference_output_type=tf.int8 ) applied to YOLOv8's output tensor. YOLOv8 packs bounding box coordinates and confidence scores into a single output tensor of shape  (1, 5, 8400) . The bbox values have a large dynamic range (~640 pixels), while the confidence scores are in the range of ~0 to 1. When the entire output tensor shares a single quantization scale, that scale is dominated by the large bbox values (~640), leaving only a fraction of one integer level to represent the entire confidence range (~1). As a result, all confidence values are effectively rounded to zero after INT8 quantization. Recommended Solution Instead of going through  onnx2quant , export INT8 TFLite directly from your trained  .pt  model using Ultralytics, then feed it into  neutron-converter : # Export INT8 TFLite directly (calibration uses your training dataset) yolo export model=best.pt \ format=litert \ imgsz=640 \ quantize=8 \ data=dataset.yaml \ fraction=0.1 # Compile for Neutron (unchanged) neutron-converter --target imx95 --input best_int8.tflite --output best_neutron.tflite For the input and output data type, please ensure they are np.int8: interp = tf.lite.Interpreter(model_path=TFLITE_INT8) interp.allocate_tensors() inp_d  = interp.get_input_details()[0] out_ds = interp.get_output_details() inp_scale, inp_zp = inp_d["quantization"] out_d = out_ds[0] out_scale, out_zp = out_d["quantization"] print(f"  Input  dtype={inp_d['dtype']}  shape={inp_d['shape'].tolist()}"       f"  quant=(scale={inp_scale:.6f}, zp={inp_zp})") print(f"  Output dtype={out_d['dtype']}  shape={out_d['shape'].tolist()}"       f"  quant=(scale={out_scale:.6f}, zp={out_zp})")# Determine input format from shape in_shape = inp_d["shape"].tolist()   # [1,3,640,640] or [1,640,640,3] if in_shape[1] == 3:     # NCHW     src=img_nchw else:     # NHWC     src=img_nhwcif inp_d["dtype"] == np.int8:     src_int8 = np.clip(np.round(src / inp_scale + inp_zp), -128, 127).astype(np.int8)     interp.set_tensor(inp_d["index"], src_int8) else:     interp.set_tensor(inp_d["index"], src.astype(np.float32))interp.invoke() raw_out = interp.get_tensor(out_d["index"])  # may be int8 or float32if out_d["dtype"] == np.int8:     dq_out = (raw_out.astype(np.float32) - out_zp) * out_scale else:     dq_out = raw_out.astype(np.float32)dq_out = dq_out[0]   # (5, 8400) normalized# Rescale bbox back to pixel coords for display BBOX_SCALE = 640.0 tfl_bbox = dq_out[:4] * BBOX_SCALE   # (4, 8400) tfl_conf = dq_out[4]                  # (8400,) Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Hi Tried the commands you shared... But neutron-converter is failing to convert the model... please find the log attached for your reference Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Please provide the log. Re: Unable to compile YOLOv8/YOLO11 TFLite models for i.MX95 Neutron NPU Hi, Please find the attached log files. I was able to successfully train the model and run it on the i.MX95 NPU. However, I noticed one observation regarding the quantization parameters: Quant: (0.003921568859368563, -128) The negative quantization zero-point value caught my attention, and I would like to confirm whether this is expected behavior. Please find the attached logs for your reference. Thank you.
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