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S32K388 RMII Reference Clock Good Morning,  I have an issue with the S32K388 on the RMII interface of a custom board.  The S32K388 is setup as the MAC and is connected to a PHY.  The issue is related with 50MHz reference clock because I want to generate it internally and send it to the PHY using the gmac1_mii_rmii_rgmii_tx_clk pin. All the examples that I have found use an external crystal oscillator (ex. S32K324 MII mode - NXP Community) but I think it is not necessarily required after reading this in the RM: I wasn't able to find in the RM how achieve it.  Any help would be appreciated! Thanks in advance! Re: S32K388 RMII Reference Clock Hi @javivalero , In theory, it is possible to generate the clock reference from the internal PLL and connect it to the gmac1_mii_rmii_rgmii_tx_clk (PTC1) pin. However this was thought for RGMII mode, not RMII. Best regards, Pavel Re: S32K388 RMII Reference Clock Hi @javivalero , what PHY are you using? Could you shared schematic of your board? Best regards, Pavel
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PT2001 Vboost LS7 G stuck on With the dram2.bin and target voltage high, I am getting constant on, so I reduced both voltage and current switching points, and no current. Documentation is unclear, I assume the Voltage levels are always effective, and a target 20V off 18V on and for 1A off 0.5A on. Note Figure 6. shows non existant D_LS7, why have we been invaded by the underscore? Safer than hyphen or minus? Who has a problem with DLS7 or LS7D? Solenoid Controller Re: PT2001 Vboost LS7 G stuck on I dont know why but writing these request really help. Revised to 20Voff 18Von, 2Aoff 1Aon, and ...... works now. 🙂
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Freemaster : How to access to registry ? I would like to know if Freemaster allows access to ARM and hardware registers during the execution of embedded code. Can we perform a memory dump of an application and thus have access to the registers, and deduce their hardware representation? Re: Freemaster : How to access to registry ? Hello,  no, you cannot sample Core registers from FreeMASTER. Sampling register values over JTAG is not supported. And in case of communication over UART, CAN or another driver, sampling register values would be quite useless as most of the values would be set to values related to the driver execution. Sampling other core registers and special registers could be useful in some cases. You would need to mirror their values to variables first (or periodically) and then sample the variables. Regards, Michal I guess it would make no sense to sample common registers as they But you can modify your application to periodically mirror them to 
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What is relation between MCUXpresso for VSCode and Zephyr? Hello, I want to start a new project with the iMXRT10xx series processor. I understand I can use MCUXpresso or VSCode with MCUXpresso for VSCode. Are they the same but just on a different IDE? Or is MCUXpresso for VSCode based on Zephyr and MCUXpressor not? Re: What is relation between MCUXpresso for VSCode and Zephyr? So when using VSCode with the extension, I can select between MCUXpress or Zephyr? If I understand correctly MCUXpress will take care of configuration of the chip resources like Uarts and I2C. To my knowledge Zephyr does the same (in a more generic way?). So I have to choose between them? Re: What is relation between MCUXpresso for VSCode and Zephyr? Hi, MCUXpresso is an ecosystem of software and tools supporting NXP devices with ARM Cortex-M (https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-:MCUXPRESSO) "MCUXpresso for VS Code" is an VS Code extension supporting NXP ARM Cortex-M devices using various software repositories, including Zephyr and MCUXpresso SDK (https://marketplace.visualstudio.com/items?itemName=NXPSemiconductors.mcuxpresso) Documentation about how to use this extension : https://github.com/nxp-mcuxpresso/vscode-for-mcux/wiki A step by step guide for using VS Code + Zephyr + RT10xx device is located here: https://github.com/nxp-mcuxpresso/vscode-for-mcux/wiki/Training-Zephyr-Getting-Started-RT1060  Regards, Cristian
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S32K344 Sensing voltage on PTA11 pin using ADC. Hello, I want to sense voltage varying from 0 to 3.3V DC on PTA11 pin of S32K344 MCU using ADC. Can someone provide me any RTD based(non-Autosar) example of that or similar example with different pin also fine. I am using Design Studio 3.5 and RTD3.0.0 Thanks. Re: S32K344 Sensing voltage on PTA11 pin using ADC. Hi @jerryrig, I have sent you a private message regarding the example. Best regards, Julián
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PT2001 Vboost LS7 Gが動かなくなる dram2.binと目標電圧が高いと、常にオンになってしまうので、電圧と電流の両方のスイッチングポイントを減らし、電流を流さないようにしました。ドキュメントは不明ですが、電圧レベルは常に有効であり、目標値は20Vオフ18Vオン、1Aオフ0.5Aオンだと思います。図6に注意してください。存在しないD_LS7を示していますが、なぜアンダースコアに侵されているのですか?ハイフンやマイナスよりも安全ですか?DLS7またはLS7Dに問題があるのは誰ですか? ソレノイドコントローラー 日時:PT2001 Vboost LS7 Gが動かなくなる なぜかはわかりませんが、これらのリクエストを書くことは本当に役に立ちます。20Voff 18Von、2Aoff 1Aon、...... に改訂現在動作します。 🙂
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u-boot splash screen (no command line messages) hello guys,  I am pretty new to this u-boot environment and customization and using i.mx 8mp board. I need some inputs or help or some steps(actually elaborated) in order to create a minimal u-boot with custom splash screen(image on entire screen) with no command line logs while booting. I have this .bmp image which I have created by following some external links. but no idea how to proceed further from there. Any help or inputs on this is highly appreciated as I know I am asking you guys a bigger chunk of help. Anil Kumar i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: u-boot splash screen (no command line messages) Hello @anilkandikonda  I hope you are doing very well. You can take a look to the AN13709 that is about of Linux Boot Time Optimizations for i.MX8M Family. In chapter 4 is mentioned the possible Bootloader optimizations. I hope this information can helps to you. Best regards, Salas.
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Freemaster : レジストリへのアクセス方法 ? Freemasterが組み込みコードの実行中にARMとハードウェアレジスタへのアクセスを許可しているかどうか知りたいです。アプリケーションのメモリダンプを実行してレジスタにアクセスし、そのハードウェア表現を推測することはできますか?
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Freemaster:如何访问注册表? 我想知道 Freemaster 是否允许在执行嵌入式代码期间访问 ARM 和硬件寄存器。我们能否执行应用程序的内存转储,从而访问寄存器并推断其硬件表示?
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imx6ull increase cpu frequency to 792MHz Hi, I built a Debian based OS with the current environment: Linux 6.6.58-rt45-0 - Mainline u-boot 2024.07 - Mainline I have a custom HW which has an imx6ull microprocessor.  I based the device tree on imx6ul-14x14-evk.dtsi (uboot and kernel). My custom device tree inherits from "imx6ull.dtsi" I would like to know if I can use 792MHz or 900MHz for CPU freq. I've seen those frequencies are available on Device Tree definition: &cpu0 {        clock-frequency = <900000000>;        operating-points = <                /* kHz  uV */                900000  1275000                792000  1225000                528000  1175000                396000  1025000                198000  950000        >;        fsl,soc-operating-points = <                /* KHz  uV */                900000  1250000                792000  1175000                528000  1175000                396000  1175000                198000  1175000        >; }; However, in my file system I do not have them available: root@imx6ull:~# cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq 528000 root@imx6ull:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies   198000 396000 528000 Does it possible? Does it limited by HW, voltage or current input?  I've seen other questions in the forum related to it but I did not find a clear answer: How to set imx6UL CPU to 528MHz in U-boot  About changing the internal LDOs voltage in i.MX6DQ.  How to set CPU frequency on u-boot?  Thanks, Javier Re: imx6ull increase cpu frequency to 792MHz Hi, Thank you both four replies. Now I understand where the limitation comes from. The partnumber is MCIMX6Y2CVM05AB, therefore it is nothing to do here. I've checked the fuses and results match with @lapohab described. Regarding the software changes... I agree with @lapohab . By default all frequencies are available in the Device Tree, therefore, if it is supported by the soc, those frequencies must appear in user space and it would be possible to change the CPU frequency in running time. There is no need to hardcode only one frequency in the Device Tree. Thanks for the support Re: imx6ull increase cpu frequency to 792MHz It has been clearly described in the last post. This cannot be burned by yourself. It is burned during production testing. I attach it again. It says "Burned by tester program, forindicating IC core speed (Hotburn may not be used)." Industrial part and Consumer part have different life times. This is in i.MX 6ULL ​​Product Usage Lifetime Estimates (AN5337). If you force a higher frequency in the software than its grade defined, the life time will inevitably be shortened. According to your idea, everyone should buy a cheaper Consumer part and burn it into an industrial part by themselves. It will save lots of money including my running projects. According to your idea, another case is just burn fuse of industrial part, it can run at 900M without life time impact. Why NXP does not have 900M industrial part? Why are there still different parts of different grades for sale? Remove the other frequencies? Have you ever tried it? Just looking at the code, it doesn't work. You can only modify the following code, but I think it is only for testing purpose. As I said before, If you force a higher frequency in the software, the life time will inevitably be shortened. if (of_machine_is_compatible("fsl,imx6ull")) { #if 0 if (val < OCOTP_CFG3_6ULL_SPEED_792MHZ) imx6x_disable_freq_in_opp(dev, 792000000); if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ) imx6x_disable_freq_in_opp(dev, 900000000); #endif } Re: imx6ull increase cpu frequency to 792MHz Hi, My idea was to remove the other frequencies before blowing the highlighted fuse. You could try to only add the 792MHz node in DTS, if not, you should modify the fuses if your part number matches the 08 code. Regards, Re: imx6ull increase cpu frequency to 792MHz All frequencies are already in the device tree. The code will determine the chip type based on different fuses and then modify the DTB in real-time. https://github.com/nxp-imx/linux-imx/blob/lf-6.6.3-1.0.0/drivers/cpufreq/imx6q-cpufreq.c #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2 #define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2 #define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3 static int imx6ul_opp_check_speed_grading(struct device *dev) { u32 val; int ret = 0; if (of_property_present(dev->of_node, "nvmem-cells")) { ret = nvmem_cell_read_u32(dev, "speed_grade", &val); if (ret) return ret; } else { struct device_node *np; void __iomem *base; np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp"); if (!np) np = of_find_compatible_node(NULL, NULL, "fsl,imx6ull-ocotp"); if (!np) return -ENOENT; base = of_iomap(np, 0); of_node_put(np); if (!base) { dev_err(dev, "failed to map ocotp\n"); return -EFAULT; } val = readl_relaxed(base + OCOTP_CFG3); iounmap(base); } /* * Speed GRADING[1:0] defines the max speed of ARM: * 2b'00: Reserved; * 2b'01: 528000000Hz; * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL; * 2b'11: 900000000Hz on i.MX6ULL only; * We need to set the max speed of ARM according to fuse map. */ val >>= OCOTP_CFG3_SPEED_SHIFT; val &= 0x3; if (of_machine_is_compatible("fsl,imx6ul")) if (val != OCOTP_CFG3_6UL_SPEED_696MHZ) imx6x_disable_freq_in_opp(dev, 696000000); if (of_machine_is_compatible("fsl,imx6ull")) { if (val < OCOTP_CFG3_6ULL_SPEED_792MHZ) imx6x_disable_freq_in_opp(dev, 792000000); if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ) imx6x_disable_freq_in_opp(dev, 900000000); } return ret; } Re: imx6ull increase cpu frequency to 792MHz Hi Josheph, I have already available that operating point in my device tree, it is defined in imx6ull.dtsi, and by default is set to 900000000Hz. I decompiled the Device Tree in my running system and I can see the same configuration: cpus { #address-cells = <0x01>; #size-cells = <0x00>; cpu@0 { compatible = "arm,cortex-a7"; clocks = <0x01 0x5d 0x01 0x1a 0x01 0x26 0x01 0xdb 0x01 0x38 0x01 0x39 0x01 0x19>; nvmem-cells = <0x04>; device_type = "cpu"; soc-supply = <0x03>; arm-supply = <0x02>; clock-names = "arm\0pll2_bus\0pll2_pfd2_396m\0secondary_sel\0step\0pll1_sw\0pll1_sys"; fsl,soc-operating-points = <0xdbba0 0x1312d0 0xc15c0 0x11edd8 0x80e80 0x11edd8 0x60ae0 0x11edd8 0x30570 0x11edd8>; phandle = <0x37>; reg = <0x00>; clock-frequency = <0x35a4e900>; // 900000000 Hz operating-points = <0xdbba0 0x137478 0xc15c0 0x12b128 0x80e80 0x11edd8 0x60ae0 0xfa3e8 0x30570 0xe7ef0>; //900000 - 1275000 ... clock-latency = <0xee6c>; #cooling-cells = <0x02>; nvmem-cell-names = "speed_grade"; }; }; However, I do not have available 792MHz nor 900MHz from user space. And the system is running at 528MHz. I have exactly the same configuration in u-boot. What you mean with "modify the dts file" Which dts file? Do you mean leave only 900MHz frequency in DTS? Thanks, Javier Re: imx6ull increase cpu frequency to 792MHz Hi, Thank you for your interest in NXP Semiconductor products, If you want to run the i.MX6ULL at exact 900MHz, then for that you need to modify the dts file. operating-points = <       /* kHz  uV */       900000  1275000 Regards
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NPU 不适用于 iMX95 大家好, 我正在研究 iMX95 EVK,并尝试在 NPU 上运行 Mobilenetv1 模型的基本示例 我得到了 NeutronDelegate 委托:31 个节点中有 0 个节点被委托,且有 0 个分区。 这意味着即使我给了 Neutron 委托,它也无法利用 NPU。 ./label_image -m mobilenet_v1_1.0_224_quant.tflite -i grace_hopper.bmp -l labels.txt --external_delegate_path=/usr/lib/libneutron_delegate.so INFO: Loaded model mobilenet_v1_1.0_224_quant.tflite INFO: resolved reporter INFO: EXTERNAL delegate created. INFO: NeutronDelegate delegate: 0 nodes delegated out of 31 nodes with 0 partitions. INFO: Applied EXTERNAL delegate. INFO: invoked INFO: average time: 16.563 ms INFO: 0.764706: 653 military uniform INFO: 0.121569: 907 Windsor tie INFO: 0.0156863: 458 bow tie INFO: 0.0117647: 466 bulletproof vest INFO: 0.00784314: 835 suit 有人可以解释一下为什么会发生这种情况吗?
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PTN3460 PTN3460可以支持把640x240分辨率的dp信号转换成640x240分辨率的lvds信号吗? Re: PTN3460 Hi chenyuan 这个分辨率不高,PTN3460可以支持到3840x2160(4K) DP1.2. Re: PTN3460 DP信号版本尚未确定,有哪个版本的是支持640*240分辨率的呢
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LPC860 MCU的LPCXpresso860-MAX开发板 使用2块LPC860 MCU的LPCXpresso860-MAX开发板, 通过 keil 分别运行 demo 程序i3c_interrupt_b2b_transfer_master 和 i3c_interrupt_b2b_transfer_slave, master 程序在SDR read 的阶段, 在MCTRL 写入 0x6180(ADDR:0x30 slaver DDA, DIR:0x01 read, IBIRESP:0x10 ACK with * mandatory byte)后, MERRWARN 值立即变为0x00000004 (I3C_MERRWARN_NACK_MASK:Not acknowledge (NACK) error), MSTATUS 值立即变为0x00009923 ,导致后续 master 接收不到 slaver 的SDR数据. 我真的不知道接下来该怎么做. 提供帮助将感激不敬. Re: LPC860 MCU的LPCXpresso860-MAX开发板 Hi @Zahi  是的 我对照了我的开发板之间的连线与你的一样。 我用的IDE 为了MCUXpresso IDE,SDK版本为2.15. 您是否可以换这个IDE尝试一下。 BR Harry Re: LPC860 MCU的LPCXpresso860-MAX开发板 是的, 烧录程序后, 关闭keil, 尝试过使用台式机或笔记本标准USB口, 未经任何hub转换, 未处于调试模式, 结果跟doc文档不一致, 均卡在 SDR READ 阶段. 请问有没有任何值得怀疑的地方呢?因为您那边看起来结果是OK的. Re: LPC860 MCU的LPCXpresso860-MAX开发板 Hi @Zahi  请问您是两个板子都是全速运行代码么? 我尝试运行一下代码,是没有问题的。 BR Harry Re: LPC860 MCU的LPCXpresso860-MAX开发板 @Harry_Zhang  调试过程如下 : Re: LPC860 MCU的LPCXpresso860-MAX开发板 Hi @Harry_Zhang  感谢回复 我用的是官方示例 然后代码调试看到 master 在SDR read 阶段 发送 I3C_MasterTransferNonBlocking 中, 给MCTRL写值后MERRWARN就变为0x00000004了 Re: LPC860 MCU的LPCXpresso860-MAX开发板 Hi @Zahi  请问您是用运行官方SDK的 I3C demo出现这个问题么? BR Harry
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NPU not working for iMX95 Hi All, I am working on iMX95 EVK and while I try to run basic example for Mobilenetv1 model on NPU  I am getting NeutronDelegate delegate: 0 nodes delegated out of 31 nodes with 0 partitions. This means its not able to utilize the NPU even after I give  Neutron delegate. ./label_image -m mobilenet_v1_1.0_224_quant.tflite -i grace_hopper.bmp -l labels.txt --external_delegate_path=/usr/lib/libneutron_delegate.so INFO: Loaded model mobilenet_v1_1.0_224_quant.tflite INFO: resolved reporter INFO: EXTERNAL delegate created. INFO: NeutronDelegate delegate: 0 nodes delegated out of 31 nodes with 0 partitions. INFO: Applied EXTERNAL delegate. INFO: invoked INFO: average time: 16.563 ms INFO: 0.764706: 653 military uniform INFO: 0.121569: 907 Windsor tie INFO: 0.0156863: 458 bow tie INFO: 0.0117647: 466 bulletproof vest INFO: 0.00784314: 835 suit Could anyone share why is that happening? Re: NPU not working for iMX95 Hello, Please try the L6.6.36 images. I don't test other version but there is no such issue on L6.6.36 images. root@imx95evk:/usr/bin/tensorflow-lite-2.16.2/examples# ./benchmark_model --graph=mobilenet_v1_1.0_224_quant.tflite --external_delegate_path=/usr/lib/libneutron_delegate.so INFO: STARTING! INFO: Log parameter values verbosely: [0] INFO: Graph: [mobilenet_v1_1.0_224_quant.tflite] INFO: External delegate path: [/usr/lib/libneutron_delegate.so] INFO: Loaded model mobilenet_v1_1.0_224_quant.tflite INFO: EXTERNAL delegate created. INFO: NeutronDelegate delegate: 29 nodes delegated out of 31 nodes with 1 partitions. INFO: Explicitly applied EXTERNAL delegate, and the model graph will be partially executed by the delegate w/ 1 delegate kernels. INFO: Created TensorFlow Lite XNNPACK delegate for CPU. INFO: The input model file size (MB): 4.27635 INFO: Initialized session in 65166.9ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=274 first=3027 curr=1831 min=1629 max=3027 avg=1776.68 std=102 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=552 first=1843 curr=1842 min=1623 max=2180 avg=1762.19 std=69 INFO: Inference timings in us: Init: 65166931, First inference: 3027, Warmup (avg): 1776.68, Inference (avg): 1762.19 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=77.3242 overall=77.3242 Best Regards, Zhiming
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PTN3460 Can PTN3460 support converting 640x240 resolution DP signal into 640x240 resolution LVDS signal?
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PTN3460 PTN3460 は、640x240 解像度の DP 信号を 640x240 解像度の LVDS 信号に変換することをサポートしますか?
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NPUがiMX95で機能しない こんにちは、皆さん。 私はiMX95 EVKに取り組んでおり、NPUでMobilenetv1モデルの基本的な例を実行しようとしています 私はNeutronDelegateデリゲートを取得しています:0パーティションを持つ31ノードのうち0ノードが委任されています。 これは、私がNeutronに委任を与えた後でもNPUを利用できないことを意味します。 ./label_image -m mobilenet_v1_1.0_224_quant.tflite -i grace_hopper.bmp -l labels.txt --external_delegate_path=/usr/lib/libneutron_delegate.so INFO: Loaded model mobilenet_v1_1.0_224_quant.tflite INFO: resolved reporter INFO: EXTERNAL delegate created. INFO: NeutronDelegate delegate: 0 nodes delegated out of 31 nodes with 0 partitions. INFO: Applied EXTERNAL delegate. INFO: invoked INFO: average time: 16.563 ms INFO: 0.764706: 653 military uniform INFO: 0.121569: 907 Windsor tie INFO: 0.0156863: 458 bow tie INFO: 0.0117647: 466 bulletproof vest INFO: 0.00784314: 835 suit なぜそれが起こっているのか、どなたか共有していただけますか?
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OV5640 and OV7251 with IMX8MM over MIPI-CSI Hi all, I know that we cannot use dual camera with MIPI-CSI as IMX8MM has only one virtual channel support. I want to use single virtual channel for two cameras. Two camera mipi lines are handled by multiplexer in hardware. So at a time only one camera will be active. I will have only one camera entry in dts file. So theoretically processor will connect with single mipi-csi camera. I have made OV5640 and OV7251 camera modules as loadable kernel module. Both will operate on single lane mipi. I will keep same compatible field, same driver file name and compile them differently. So I will have two ex. "cam.ko" files with same compatible field but different driver code inside. I can rename few function names if needed. Q.1) is this achievable? I have tried loading loadable kernel module after kernel bootup. When I insert it manually it gets register with MIPI-CSI. While removing with "rmmod" it gives error as "rmmod: ERROR: Module cam.ko is builtin" Q.2) How can we de-register / remove kernel module so that another kernel module can get inserted? Switching between two kernel with selection of multiplexer channel will be done by user application. Thanks, Ajita #IMX8MM MIPI-CAMERA  #LINUX i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: OV5640 and OV7251 with IMX8MM over MIPI-CSI Hi @Chavira , I have successfully implemented single virtual channel for two cameras. Two camera MIPI lines are handled by multiplexer in hardware. So at a time only one camera will be active. DTS contains only one entry of camera as follow: ov5640_mipi: ov5640@70 { #compatible = "ovti,ov5640"; compatible = "ovti,ov5640_mipi"; reg = <0x70>; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst_ov7251>, <&pinctrl_csi_led>; clocks = <&clk IMX8MM_CLK_CLKO1>; #clock-names = "xclk"; clock-names = "csi_mclk"; assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; assigned-clock-parents = <&clk IMX8MM_CLK_24M>; assigned-clock-rates = <24000000>; csi_id = <0>; //reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; clock-frequency = <24000000>; #csi_mclk = <24000000>; mclk = <24000000>; mclk_source = <0>; port { ov5640_mipi1_ep: endpoint { remote-endpoint = <&ov5640_0_ep>; clock-lanes = <0>; data-lanes = <1>; }; }; }; &mipi_csi_1 { #address-cells = <1>; #size-cells = <0>; status = "okay"; port { ov5640_0_ep: endpoint@1 { remote-endpoint = <&ov5640_mipi1_ep>; data-lanes = <1>; csis-hs-settle = <13>; csis-clk-settle = <2>; csis-wclk; }; csi1_mipi_ep: endpoint@2 { remote-endpoint = <&csi1_ep>; }; }; }; 0x70 is I2C address of OV7251. Change OV5640's I2C address in it's probe function to 0x3C and In it's remove function again assign address back to 0x3C. Make reset changes according to dts in both files. Both OV5640 and OV7251 must have same reset, pwn and MIPI lanes common. : Make "CONFIG_MODULE_FORCE_UNLOAD" flag enable in menuconfig and "CONFIG_MXC_CAMERA_OV5640_MIPI_V2" as m. First compile code for OV5640. Keep generated "ov5640_camera_mipi_v2.ko" aside. Now Copy OV7251's driver code in OV5640's file. Keep compatible same as OV5640's compatible name. Rename generated "ov5640_camera_mipi_v2.ko" to "ov7251.ko". Copy these two kernel modules to IMX8MM. To insert kernel module use "insmod " and for removal "rmmod -f ov5640_camera_mipi_v2". Use mux's select line accordingly. Use one camera at a time on "/dev/video0". I know this is standard way but It works 😉 Thanks, Ajita Re: OV5640 and OV7251 with IMX8MM over MIPI-CSI HI @ajita02! This is the only post that we have for the use case that you want to achieve.   Best regards! Chavira   Re: OV5640 and OV7251 with IMX8MM over MIPI-CSI Hi, Mentioned link won't work as it is with respect to IMX8MP which has two MIPI-CSI interface. We have tried this link before posting this issue. Those mentioned files/controller is not present on IMX8MM. IMX8MM cannot register two endpoints.   Thanks, Ajita Re: OV5640 and OV7251 with IMX8MM over MIPI-CSI HI @ajita02! Thank you for contacting NXP Support! We don´t have documentation for that specific use case but you can take as a reference the next community post where we bring up dual Camera under single mipi csi using the iMX8MP with OV5640 + os08a20. https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/bring-up-dual-Camera-under-single-mipi-csi/ta-p/1728321 Best Regards! Chavira
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S32K148 MCAL和GHS编译器 你好 我们在 Autosar 项目中使用 S32K148 MCAL RTM 4.0 1.0.4,使用 Greenhills 编译器工具链。 我们遇到了一些性能问题,并希望将编译器优化级别提高到-Ospeed ,以尽可能提高性能。 我们需要 NXP 提供的是,是否已经使用 MCAL 加 Greenhills 编译器加高优化进行过任何验证?这可以涵盖任何必要的变量声明(例如volatile等)。 此致敬礼 回复:S32K148 MCAL和GHS编译器 [elxr](错误 #16)找不到文件 rcsD 文件 我收到此错误,该如何解决?我正在使用带有 ghs 编译器的 bazel 构建系统,目标是 S32GA
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How many CAN channels are supported by the MPC5748G EVB? Hello Team, I am using MPC5748G EVB for one of my projects. I want to interface 2 CAN channels, but I observed that the MPC5748G EVB has only one CAN. Could you please tell me how many CAN channels are supported by the MPC5748G EVB? Please provide the pin diagram for MPC5748G EVB. Re: How many CAN channels are supported by the MPC5748G EVB? No. I did not Re: How many CAN channels are supported by the MPC5748G EVB? Hi@Anilpatil_Sasva Auto You need additional CAN THY hardware interface, but generally no such hardware exists Re: How many CAN channels are supported by the MPC5748G EVB? Kindly suggest how to use 2 CAN channels with the MPC5748G board. Let me know if there are any alternative methods. Re: How many CAN channels are supported by the MPC5748G EVB? Hi@Anilpatil_Sasva Auto The hardware of MPC5748G EVB has only one CAN PTH, which only supports CAN0. Re: How many CAN channels are supported by the MPC5748G EVB? As per the reference manual, a total of 8 Flexcan channels are available, I need to use 2 CAN channels with the Evaluation board, kindly confirm. Re: How many CAN channels are supported by the MPC5748G EVB? Hi@Anilpatil_SasvaAuto   you can find all the details in the link below. https://www.nxp.com/document/guide/getting-started-with-the-devkit-mpc5748g:NGS-DEVKIT-MPC5748G
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