S9KEAZ series into MCUXPRESSO Dear All. Is it a way to create a project into MCUXpresso for the S9KEAZN32ACLC MCU? I mean, using the standard way that is to create a SDK and build overt it? OR, maybe, by using the "generic M0+" entry? Hints welcome. Best regards. Jorgecon Re: S9KEAZ series into MCUXPRESSO Thanks, Zhang. It is clear. Re: S9KEAZ series into MCUXPRESSO Hello Jorgecon, MCUXPRESSO doesn't support S9KEAZ series. This series is automotive MCU which is supported by S32DS https://www.nxp.com/design/design-center/software/automotive-software-and-tools/s32-design-studio-ide/s32-design-studio-for-arm:S32DS-ARM the related BSP and drivers are under  "Embedded Software" of this page https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/automotive-mcus/ultra-reliable-kea-automotive-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:KEA Hope this helps, Jun Zhang

MPC5777C - Questions about the PRAMC (late-write buffer and bursts) Hello! I have two questions about the PRAMC: 1 - What happens when the caches of different cores request different data that belongs to the same cache line? The XBAR requests two bursts wrapped in a different order or the SRAM services the same burst to both cores and the XBAR sends a copy of the burst to each core? If the XBAR sends the same burst to both cores, in which order are the words in this burst wrapped? The word requested from which core will be serviced first in the burst request? 2 - When is the late-write buffer emptied? When it is full or when it is already full and the PRAMC tries to put more data in it? The question that I am trying to answer is if there is the possibility of a core performing a write operation and, because of the late-write buffer being full, the core write latency is increased with the entire latency of the late-write buffer being emptied. Best regards, Matheus Re: MPC5777C - Questions about the PRAMC (late-write buffer and bursts) 1) Not sure what you mean by different data. I suppose you mean ‘different address’ belonging to the same line. Also I suppose you are discussing situation when other ways of cache are full. 1a) As you already know, Internal SRAM is split into two halves, each accesses over different port: PRAMC_0 - Slave Port 2 - Address[31:18] = 0100_0000_0000_00b PRAMC_1 - Slave Port 4 - Address[31:18] = 0100_0000_0000_01b Both accesses may run in parallel, there is no issue. 1b) If both accesses goes over same port, firstly started access is executed first (if both triggered simultaneously then started according priority). Burst access cannot be interrupted, it is locked transfer with longest access time. Firstly burst access from one core happens and then burst access from another core. 2) RAM says “In the case of back-to-back writes, the write may be forced to bypass the late-write buffer and instead be stored directly, precisely in the RAM.” In other words, if late write buffer is full and another write happens, this write is processed first and then late-write buffer is emptied.

S32K344 オフラインフラッシュ AB パーティション こんにちは、 S32K344はABパーティションのオフラインフラッシュを実装できますか？何か手順や方法はありますか？ ありがとう Re: S32K344 オフラインフラッシュ AB パーティション どうやってそれをやったんですか、友達？

S9KEAZシリーズをMCUXPRESSOに 親愛なる皆さん。 これは、S9KEAZN32ACLC MCU用のプロジェクトをMCUXpressoに作成する方法ですか?つまり、SDKを作成し、それを明白にビルドするという標準的な方法を使用しているのでしょうか? それとも、「generic M0+」エントリを使用するのでしょうか? ヒントは大歓迎です。 よろしくお願いいたします。 ジョルジェコン Re:MCUXPRESSOにS9KEAZシリーズ ありがとう、張。それは明らかです。 Re:MCUXPRESSOにS9KEAZシリーズ こんにちは、ジョルジェコン、 MCUXPRESSOはS9KEAZシリーズをサポートしていません。S32DSに対応した車載用マイコンです https://www.nxp.com/design/design-center/software/automotive-software-and-tools/s32-design-studio-ide/s32-design-studio-for-arm:S32DS-ARM 関連する BSP とドライバは、このページの「組み込みソフトウェア」にあります https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/automotive-mcus/ultra-reliable-kea-automotive-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:KEA お役に立てば幸いです。 張 俊

无法安装更新[代理连接问题] 我正在尝试下载并安装 S32G 系列的扩展/更新，它显示可用的更新和扩展，但当我选择安装它们时，它尝试下载，但一段时间后显示以下错误， 我在公司网络上，可以毫无问题地连接到互联网 我可以在哪里为 S32 Design Studio 设置此代理？ 回复：无法安装更新[代理连接问题] 我已经完成代理设置，现在可以正常工作了 回复：无法安装更新[代理连接问题] 这是错误信息[附件]

リセット後の TLB1 エントリ 0 値 (e5500 コア) e5500 コアのリファレンス マニュアルによると、リセット後に TLB1 エントリがあります。また、リアルページ番号(RPN)の上位6ビットがSoCによってコアに適用されることも示されています。ただし、T1040リファレンスマニュアルでは、これらの6ビットに関する具体的な詳細は見つかりませんでした。T1040 SoCの6ビット値について教えてください。この情報は、不足している場合は T1040 SoC のドキュメントに追加すると役立つ場合があります。 ありがとうございます。 Re:リセット後のTLB1エントリ0値(e5500コア) あなたの提案をありがとう、私たちはします。 Re:リセット後のTLB1エントリ0値(e5500コア) なぜこの情報がt1040リファレンスマニュアルにないのですか。この情報は、次の改訂のためにマニュアルに追加できます。 感謝。 Re:リセット後のTLB1エントリ0値(e5500コア) この情報は、AEチームから提供された内部データベースから取得しました。 Re:リセット後のTLB1エントリ0値(e5500コア) @yipingwang 情報をいただきありがとうございますが、リファレンス マニュアルのどこで見つけたかを参照していただけますか? 「00011」であることも知っていましたが、リファレンス マニュアルには記載されていません。リファレンス マニュアルのセクションを参照してください。 Re:リセット後のTLB1エントリ0値(e5500コア) リセット後の TLB1 エントリ 0 のデフォルトの RPN[28-51] は fffff です。したがって、RPN[28-33] は "000011" です。

S32K314-Q257 MBDT support does the MBDT support the S32K314-Q257 processor? it isn't on the list. is it possible to use the S32K344-Q257 configuration for the S32K314-Q257 processor? if not, are there plans to add this processor? is there another work around? Re: S32K314-Q257 MBDT support Hi @Deskwork4130  For using the S32K314-Q257 processor, first of all you would need to select the S32K314 option inside the Hardware Part dropdown of the model's configuration parameters, as illustrated below. Even if this selection refers to a different processor package (172 pins), this selection will ensure that during the Simulink model build process, S32K314 specific files will be used. Indeed, we do not provide a configuration project for the S32K314-Q257 package, so you would need to create your own, based on the hardware that you are using. Pins, peripherals and clocks must be configured according to your setup and the particularities of the application that you would like to develop. Hence, you could start from the S32K344-Q257 default project by changing the processor to match your selection, if the settings in that project are similar to your needs. For a description on how this can be achieved, in either S32 Configuration Tools, or EB Tresos, please check the following thread. After you create a configuration project for your processor, with the necessary settings, you could use it as a Configuration Template for the models you will develop. For more details on this Configuration Template functionality, could you please check this link providing brief details on how this can be achieved and a reference to the MBDT documentation? Let us know if this helps and if any additional details are needed from our side, Irina

EEPROMデータ書込みS32K116 こんにちは、 FlexRAM APIを使用せずにEEPROMのフラッシュ領域にデータを書き込む方法があるかどうかを尋ねたかっただけです 又は EEPROMにデータを直接書き込む方法はありますか?私はフラッシュパーティションの既存の例を見てきましたがS32K116そこでは実りあるものは見つかりませんでした。 S32K116ボードのEEPROMのPフラッシュ領域にデータを書き込む手順が出てくるといいですね。 提案/返信を待っています ありがとうございます。 Re: S32K116 EEPROM データ書き込み Hi@White-アライグマ いいえ、S32 DSにはそのような機能はありません。 Re: S32K116 EEPROM データ書き込み SEGGERでも同じですか? Re: S32K116 EEPROM データ書き込み Hi@White_Racoon あなたはこの記事を見ることができます、それがあなたに役立つことを願っています。 https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/Example-S32K144-EEEPROM-usage/ta-p/1109405

S32K314-Q257 MBDT対応 MBDT は S32K314-Q257 プロセッサをサポートしていますか?リストにはありません。S32K314-Q257プロセッサにS32K344-Q257構成を使用することは可能ですか?もしそうでなければ、このプロセッサを追加する予定はありますか?別の回避策はありますか?

EVK での i.MX8MPlus Cortex-M7 コアのデバッグ 皆さん、こんにちは。 私は、i.MX 8M PlusのCortex-M7コアの開発およびデバッグ環境のセットアップに取り組んでいます。オンラインのNXP SDKビルダーツールを使用してSDKを正常に生成し、NXP MCUXpresso VSCodeプラグインを使用してFreeRTOS hello worldの例を開いてビルドすることができます。ただし、EVKで i.MX 8M Plusをフラッシュまたはデバッグすることはできませんでした。 J-Link Commander を rev 1.2 J-Link Ultra で使用して SWD 通信が機能していることを確認できましたが、Segger はこのハードウェア リビジョンでの Cortex-M7 コアのデバッグをサポートしていないため、フラッシュやデバッグができませんでした。その後、NXP MCU-Link Proデバッガを注文しましたが、デバッグにも問題があります。 NXP MCU-Link Proは、i.MX 8M PlusのCortex-M7コアをデバッグできる必要がありますか? そうでない場合、i.MX 8M Plus の Cortex-m7 コアの JTAG または SWD デバッグをサポートする既知のデバッグ プローブは何ですか。 日時: EVK での i.MX8MPlus Cortex-M7 コアのデバッグ J-Trace Cortexを注文したところ、無事にデバッグできました。また、AN14120 .pdfのセクション4に従わなければなりませんでしたリセットせずにデバッグするために上記にリンクしました。

S32K314-Q257 MBDT支持 MBDT 是否支持 S32K314-Q257 处理器？它不在列表中。是否可以将 S32K344-Q257 配置用于 S32K314-Q257 处理器？如果没有，是否有计划添加此处理器？还有其他解决方法吗？

S32k3xx SRR bug Hi, Customer: IO Controls Part: S32K3xx  I am working with a customer switching from MPC5747G to the S32K3xx MCU  since MPC5748 lacks the feature to set the “CAN messages ID” as the FCAN receive/send MBDT block input. There seems to be an issue in the SDK for the S32k1xx. When the CAN id is an extended id, the SRR bit must be set.  But the SDK generates the SRR bit as cleared.  I have attached the link of the previous post here: How to set S32K CAN bit-SRR to 1 - NXP Community I have not been able to confirm if this bug has been fixed, has it been resolved? If it has not been resolved for the S32K1xx, is it also an issue on the S32K3xx? Thanks, Brendan Re: S32k3xx SRR bug Hi Brendan, Chapter 2.2 List of fixed issues from S32K1xx RTM 4.0.2. of S32SDK_for_S32K1xx_RTM_4.0.3_ReleaseNotes.pdf mentioned can_pal CAN extended message TX, SRR bit wrong configuration. This bug has been fixed. It's not an issue on the S32K3xx. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

S32K116 EEPROM数据写入 你好呀， 我只是想问你，是否有任何可能的方法可以在不使用 FlexRAM API 的情况下将数据写入 EEPROM 的闪存区域 或者 有没有直接的方法将数据写入 EEPROM ？我已经查看了 S32K116 闪存分区的现有示例，但没有发现任何有用的信息。 如果我知道在 S32K116 板的 EEPROM 的 P 闪存区域写入数据的步骤，那就太好了。 等待建议/回复 谢谢！ 回复：S32K116 EEPROM数据写入 你好@White-Racoon 不，S32 DS 中没有此功能。 回复：S32K116 EEPROM数据写入 SEGGER 也会这样吗？ 回复：S32K116 EEPROM数据写入 你好@White_Racoon 你可以看看这篇文章，希望它对你有用。 https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/Example-S32K144-EEEPROM-usage/ta-p/1109405

Debugging an i.MX8MPlus Cortex-M7 core on the EVK. Hello all, I am working on setting up my development and debugging environment for the Cortex-M7 core of the i.MX 8M Plus.  I have successfully generated an SDK using the online NXP SDK builder tool, and I am able to open and build the FreeRTOS hello world example using the NXP MCUXpresso VSCode plugin.  However, I have not been able to flash or debug the i.MX 8M Plus on my EVK. I was able to use J-Link Commander with a rev 1.2 J-Link Ultra to confirm SWD communication was working, but I was unable to flash or debug, as Segger does not support debugging Cortex-M7 cores with this hardware revision.  I have since ordered an NXP MCU-Link Pro debugger, but I am having issues getting debugging going with that as well. Should the NXP MCU-Link Pro be able to debug the Cortex-M7 core of an i.MX 8M Plus? If not, what debugging probes are known to support JTAG or SWD debugging the Cortex-m7 core of an i.MX 8M Plus? Re: Debugging an i.MX8MPlus Cortex-M7 core on the EVK. I ordered a J-Trace Cortex and was able to debug successfully. I also had to follow section 4 of the AN14120 .pdf you linked above to debug without reset. Re: Debugging an i.MX8MPlus Cortex-M7 core on the EVK. Hi, Thank you for your interest in NXP Semiconductor products, I have a reference of a j-link plus working, do you have one handy to test it? Could you please follow the guide attached and pass the record with pro and possibly with plus? Notice that also in this post is stated that it's worked with plus. Regards

在 EVK 上调试 i.MX8MPlus Cortex-M7 内核。 大家好， 我正在为 i.MX 8M Plus 的 Cortex-M7 内核设置开发和调试环境。我已经使用在线 NXP SDK 构建器工具成功生成了一个 SDK，并且能够使用 NXP MCUXpresso VSCode 插件打开和构建 FreeRTOS hello world 示例。但是，我无法在我的 EVK 上刷新或调试 i.MX 8M Plus。 我能够使用带有 rev 1.2 J-Link Ultra 的 J-Link Commander 来确认 SWD 通信是否正常工作，但我无法进行闪存或调试，因为 Segger 不支持使用此硬件版本调试 Cortex-M7 内核。此后，我订购了 NXP MCU-Link Pro 调试器，但在使用它进行调试时也遇到了问题。 NXP MCU-Link Pro 是否能够调试 i.MX 8M Plus 的 Cortex-M7 内核？ 如果没有，哪些调试探针支持 JTAG 或 SWD 调试 i.MX 8M Plus 的 Cortex-m7 内核？ 回复：在 EVK 上调试 i.MX8MPlus Cortex-M7 内核。 我订购了 J-Trace Cortex 并且能够成功调试。我还必须遵循 AN14120 .pdf 的第 4 部分您上面链接的是在没有重置的情况下进行调试。

S32K116 EEPROM Data Write Hi There, I just wanted to ask you if there is any possible way to write data on the flash area of EEPROM without using FlexRAM api  or  Is there any direct way to write data on EEPROM ? I've gone through existing Example of S32K116 flash partition but didn't find anything fruitful over there. It would be great if I got steps to write data in the P flash area of the EEPROM of the S32K116 board. Waiting for suggestions / reply Thank you. Re: S32K116 EEPROM Data Write Hi@White-Racoon No, there is no such feature available in S32 DS. Re: S32K116 EEPROM Data Write Will it be same for SEGGER ?  Re: S32K116 EEPROM Data Write Hi@White_Racoon you can take a look at this article, hope it useful to you. https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/Example-S32K144-EEEPROM-usage/ta-p/1109405

IMX93-A55 and M33 started at the same time M core cannot control the GPIO A core SDK version ：6.1.55 M core SDK version：2.14 The first test：using flash.bin（make by make SOC=iMX9 flash_singleboot_m33） to start both A and M cores，then M core cannot control the GPIO（Test using M-core GPIO routine），However, other peripherals such as the SPI IIC work properly The secord：using flash.bin（make by make SOC=iMX9 flash_singleboot） to start A cores，start M kernel using elf link file，then The M core can control GPIO normally The third：In the uboot phase, load the firmware for gpio control (.bin format) to m33 and run m33 to control gpio normally The above test methods are based on IMX93-EVK test，Do you have the general idea and solution of the positioning problem? Thank you #IMX9352 Re:IMX93-A55とM33が同時に起動し、MコアがGPIOを制御できない ありがとうございました。この方向でテストを続けていきます。また、以下の質問にも非常に興味があります https://community.nxp.com/t5/i-MX-Processors/How-to-extend-the-buffer-size-of-A55-in-iMX9352-when-using/m-p/1764431/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufExQSFBUTEFUVTRDVlZ8MTc2NDQzMXxTVUJTQ1JJUFRJT05TfGhL  Re:IMX93-A55とM33が同時に起動し、MコアがGPIOを制御できない MコアGPIOルーチンに5秒の遅延を追加することで、あなたの指摘を確認しました（RGPIO_PININIT RMを読み取ると、AコアのATFセキュリティモジュールの初期化が完了した後、MコアのGPIO制御が必要と思われるのですが、これは正しいですか?「はい」の場合、ATF モジュールの初期化成功によって判断できるもの Re:IMX93-A55とM33が同時に起動し、MコアがGPIOを制御できない 最初のテスト:flash.bin(make by make SOC=iMX9 flash_singleboot_m33)を使用してAコアとMコアの両方を起動すると、MコアはGPIOを制御できません(MコアGPIOルーチンを使用してテスト)が、SPI IICなどの他のペリフェラルは正常に動作します --> test1 と test2&3 の違いは、test1 が A55 ファームウェアをロードする前に M33 ファームウェアをロードすることです。お使いのMコアGPIOルーチンのルールを確認してください、あなたが使用している現在のMコアGPIOルーチンは、M33コアの前にA55ファームウェアをロードする必要があるかもしれません。 Re:IMX93-A55とM33が同時に起動し、MコアがGPIOを制御できない Hi @ChumingYang  おっしゃる通りです。 「はい」の場合、ATF モジュールの初期化成功によって判断できるもの ●> GPIO_BASE+ 0x10/ 0x14/ 0x18/--> 0x1cのステータス を読み取ってみることができます 。

使用具有 3 个接口的 PFEng 驱动程序 我在 Linux 中使用带有 NXP PFEng 驱动程序的三个 SGMII 接口。我可以让其中两个（PFE1 + PFE2）加载并运行，但第三个（PFE0）无法被驱动程序识别。 它说“HIF0 未配置，已跳过”，但据我所知，它已绑定到 PFE0 并且配置与其他相同。 这是设备树， // SPDX-License-Identifier: GPL-2.0 /* * Copyright 2022-2023 NXP * */ #include #include #include #include #include / { aliases { ethernet0 = &pfe_netif0; ethernet1 = &pfe_netif1; ethernet2 = &pfe_netif2; }; soc { pfe: pfe@46000000 { compatible = "nxp,s32g-pfe"; reg = <0x0 0x46000000 0x0 0x1000000>, <0x0 0x4007ca00 0x0 0x100>; reg-names = "pfe-cbus", "s32g-main-gpr"; #address-cells = <1>; #size-cells = <0>; interrupt-parent = <&gic>; interrupts = , , , , , ; interrupt-names = "hif0", "hif1", "hif2", "bmu", "upegpt", "safety"; resets = <&reset S32CC_SCMI_RST_PART2>; reset-names = "pfe_part"; clocks = <&clks S32G_SCMI_CLK_PFE_AXI>, <&clks S32G_SCMI_CLK_PFE_PE>, <&clks S32G_SCMI_CLK_PFE_TS>; clock-names = "pfe_sys", "pfe_pe", "pfe_ts"; nvmem-cells = <&pfe_emacs_intf_sel>, <&pfe_coh_en>, <&pfe_pwr_ctrl>, <&pfe_genctrl3>; nvmem-cell-names = "pfe_emacs_intf_sel", "pfe_coh_en", "pfe_pwr_ctrl", "pfe_genctrl3"; // serdes, phy type, instance, lane phys = <&serdes1 PHY_TYPE_XPCS 0 0>, // pfe0 connected to sgmii1, lane 0 <&serdes1 PHY_TYPE_XPCS 1 1>, // pfe1 connected to sgmii1, lane 1 <&serdes0 PHY_TYPE_XPCS 1 1>; // pfe2 connected to sgmii0, lane 1 phy-names = "emac0_xpcs", "emac1_xpcs", "emac2_xpcs"; dma-coherent; memory-region = <&pfe_reserved_bmu2>, <&pfe_reserved_rt>, <&pfe_reserved>, <&pfe_reserved_bdr>; memory-region-names = "pfe-bmu2-pool", "pfe-rt-pool", "pfe-shared-pool", "pfe-bdr-pool"; nxp,fw-class-name = "s32g_pfe_class.fw"; nxp,fw-util-name = "s32g_pfe_util.fw"; nxp,pfeng-ihc-channel = ; status = "okay"; /* MDIO on PFE0 */ pfe_mdio0: mdio@0 { compatible = "nxp,s32g-pfe-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0>; status = "okay"; pfe_mdiob_phy0: ethernet-phy@0 { reg = <0>; ti,op-mode = ; }; }; /* MDIO on PFE1 */ pfe_mdio1: mdio@1 { compatible = "nxp,s32g-pfe-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <1>; status = "okay"; pfe_mdiob_phy1: ethernet-phy@0 { reg = <0>; ti,op-mode = ; }; }; /* MDIO on PFE2 */ pfe_mdio2: mdio@2 { compatible = "nxp,s32g-pfe-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <2>; status = "okay"; pfe_mdiob_phy2: ethernet-phy@0 { reg = <0>; ti,op-mode = ; }; }; /* Network interface 'pfe0' */ pfe_netif0: ethernet@10 { compatible = "nxp,s32g-pfe-netif"; status = "okay"; reg = <10>; local-mac-address = [ 00 04 9F BE EF 00 ]; nxp,pfeng-if-name = "pfe0"; nxp,pfeng-hif-channels = ; nxp,pfeng-linked-phyif = ; clocks = <&clks S32G_SCMI_CLK_PFE0_TX_SGMII>, <&clks S32G_SCMI_CLK_PFE0_TX_RGMII>, <&clks S32G_SCMI_CLK_PFE0_TX_RMII>, <&clks S32G_SCMI_CLK_PFE0_TX_MII>, <&clks S32G_SCMI_CLK_PFE0_RX_SGMII>, <&clks S32G_SCMI_CLK_PFE0_RX_RGMII>, <&clks S32G_SCMI_CLK_PFE0_RX_RMII>, <&clks S32G_SCMI_CLK_PFE0_RX_MII>; clock-names = "tx_sgmii", "tx_rgmii", "tx_rmii", "tx_mii", "rx_sgmii", "rx_rgmii", "rx_rmii", "rx_mii"; phy-mode = "sgmii"; managed = "in-band-status"; }; /* Network interface 'pfe1' */ pfe_netif1: ethernet@11 { compatible = "nxp,s32g-pfe-netif"; status = "okay"; reg = <11>; local-mac-address = [ 00 04 9F BE EF 01 ]; nxp,pfeng-if-name = "pfe1"; nxp,pfeng-hif-channels = ; nxp,pfeng-linked-phyif = ; clocks = <&clks S32G_SCMI_CLK_PFE1_TX_SGMII>, <&clks S32G_SCMI_CLK_PFE1_TX_RGMII>, <&clks S32G_SCMI_CLK_PFE1_TX_RMII>, <&clks S32G_SCMI_CLK_PFE1_TX_MII>, <&clks S32G_SCMI_CLK_PFE1_RX_SGMII>, <&clks S32G_SCMI_CLK_PFE1_RX_RGMII>, <&clks S32G_SCMI_CLK_PFE1_RX_RMII>, <&clks S32G_SCMI_CLK_PFE1_RX_MII>; clock-names = "tx_sgmii", "tx_rgmii", "tx_rmii", "tx_mii", "rx_sgmii", "rx_rgmii", "rx_rmii", "rx_mii"; phy-mode = "sgmii"; managed = "in-band-status"; }; /* Network interface 'pfe2' */ pfe_netif2: ethernet@12 { compatible = "nxp,s32g-pfe-netif"; status = "okay"; reg = <12>; local-mac-address = [ 00 04 9F BE EF 02 ]; nxp,pfeng-if-name = "pfe2"; nxp,pfeng-hif-channels = ; nxp,pfeng-linked-phyif = ; clocks = <&clks S32G_SCMI_CLK_PFE2_TX_SGMII>, <&clks S32G_SCMI_CLK_PFE2_TX_RGMII>, <&clks S32G_SCMI_CLK_PFE2_TX_RMII>, <&clks S32G_SCMI_CLK_PFE2_TX_MII>, <&clks S32G_SCMI_CLK_PFE2_RX_SGMII>, <&clks S32G_SCMI_CLK_PFE2_RX_RGMII>, <&clks S32G_SCMI_CLK_PFE2_RX_RMII>, <&clks S32G_SCMI_CLK_PFE2_RX_MII>; clock-names = "tx_sgmii", "tx_rgmii", "tx_rmii", "tx_mii", "rx_sgmii", "rx_rgmii", "rx_rmii", "rx_mii"; phy-mode = "sgmii"; managed = "in-band-status"; }; }; }; }; 这是驱动程序加载时 Linux 打印的内容， [ 1.139965] phy-s32cc-serdes 40480000.serdes: Using mode 2 for SerDes subsystem [ 1.150978] phy-s32cc-serdes 40480000.serdes: Unstable RX detected on XPCS1 [ 1.151314] phy-s32cc-serdes 44180000.serdes: Using mode 3 for SerDes subsystem [ 1.157428] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS1 [ 1.157446] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS0 ... [ 15.457853] pfeng: loading out-of-tree module taints kernel. [ 15.469032] pfeng 46000000.pfe: PFEng ethernet driver loading ... [ 15.469046] pfeng 46000000.pfe: Version: 1.3.0 [ 15.469050] pfeng 46000000.pfe: Driver commit hash: M4_DRIVER_COMMIT_HASH [ 15.469054] pfeng 46000000.pfe: Multi instance support: disabled (standalone) [ 15.469058] pfeng 46000000.pfe: Compiled by: 12.3.0 [ 15.469085] pfeng 46000000.pfe: Cbus addr 0x46000000 size 0x1000000 [ 15.469093] pfeng 46000000.pfe: nxp,fw-class-name: s32g_pfe_class.fw [ 15.469098] pfeng 46000000.pfe: nxp,fw-util-name: s32g_pfe_util.fw [ 15.469151] pfeng 46000000.pfe: netif name: pfe1 [ 15.469158] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:01 [ 15.469166] pfeng 46000000.pfe: netif(pfe1) linked phyif: 1 [ 15.469171] pfeng 46000000.pfe: netif(pfe1) mode: std [ 15.469184] pfeng 46000000.pfe: netif(pfe1) HIFs: count 1 map 02 [ 15.469192] pfeng 46000000.pfe: SGMII AN enabled on EMAC1 [ 15.469196] pfeng 46000000.pfe: EMAC1 PHY less SGMII [ 15.469204] pfeng 46000000.pfe: EMAC1 interface mode: 4 [ 15.469345] pfeng 46000000.pfe: netif name: pfe2 [ 15.469351] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:02 [[ 15.469356] pfeng 46000000.pfe: netif(pfe2) linked phyif: 2 15.469361] pfeng 46000000.pfe: netif(pfe2) mode: std [[ 15.469373] pfeng 46000000.pfe: netif(pfe2) HIFs: count 1 map 04 0[ 15.469380] pfeng 46000000.pfe: SGMII AN enabled on EMAC2 ;[ 15.469384] pfeng 46000000.pfe: EMAC2 PHY less SGMII 3[ 15.469389] pfeng 46000000.pfe: EMAC2 interface mode: 4 2[ 15.469459] pfeng 46000000.pfe: HIF channels mask: 0x0006 m[ 15.469502] pfeng 46000000.pfe: PFE port coherency enabled, mask 0x1e [ 15.469760] pfeng 46000000.pfe: Clocks: sys=300MHz pe=600MHz [ 15.469775] pfeng 46000000.pfe: Interface selected: EMAC0: 0xffffffff EMAC1: 0x4 EMAC2: 0x4 O[ 15.470473] pfeng 46000000.pfe: PFE controller reset done K[ 15.470543] pfeng 46000000.pfe: TX clock on EMAC1 for interface sgmii installed [ 15.470577] pfeng 46000000.pfe: RX clock on EMAC1 for interface sgmii installed [ 15.470629] pfeng 46000000.pfe: TX clock on EMAC2 for interface sgmii installed 15.470662] pfeng 46000000.pfe: RX clock on EMAC2 for interface sgmii installed [[ 15.470842] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34000000 0[ 15.470898] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34080000 m[ 15.470955] pfeng 46000000.pfe: assigned reserved memory node pfebufs@83200000 ][ 15.470982] pfeng 46000000.pfe: assigned reserved memory node pfebufs@835e0000 [ 15.476294] pfeng 46000000.pfe: Firmware: CLASS s32g_pfe_class.fw [45040 bytes] F[ 15.476304] pfeng 46000000.pfe: Firmware: UTIL s32g_pfe_util.fw [23252 bytes] i[ 15.476316] pfeng 46000000.pfe: [pfe_platform_master.c:3629] PFE CBUS p0x46000000 mapped @ v0xffffffc00c000000 (0x1000000 bytes) n[ 15.476324] pfeng 46000000.pfe: [pfe_platform_master.c:3634] HW version 0x101 i[ 15.476332] pfeng 46000000.pfe: [pfe_hw_feature.c:93] Silicon S32G3 s[ 15.476340] pfeng 46000000.pfe: [pfe_platform_master.c:3646] Fail-Stop mode disabled h[ 15.479186] pfeng 46000000.pfe: [pfe_platform_master.c:2783] PFE_ERRORS:Parity instance created e[ 15.479197] pfeng 46000000.pfe: [pfe_platform_master.c:2798] PFE_ERRORS:Watchdog instance created d[ 15.479203] pfeng 46000000.pfe: [pfe_platform_master.c:2814] PFE_ERRORS:Bus Error instance created [ 15.479208] pfeng 46000000.pfe: [pfe_platform_master.c:2827] PFE_ERRORS:FW Fail Stop instance created 15.479214] pfeng 46000000.pfe: [pfe_platform_master.c:2840] PFE_ERRORS:Host Fail Stop instance created [ 15.457853] pfeng: loading out-of-tree module taints kernel. [ 15.469032] pfeng 46000000.pfe: PFEng ethernet driver loading ... [ 15.469046] pfeng 46000000.pfe: Version: 1.3.0 [ 15.469050] pfeng 46000000.pfe: Driver commit hash: M4_DRIVER_COMMIT_HASH [ 15.469054] pfeng 46000000.pfe: Multi instance support: disabled (standalone) [ 15.469058] pfeng 46000000.pfe: Compiled by: 12.3.0 [ 15.469085] pfeng 46000000.pfe: Cbus addr 0x46000000 size 0x1000000 [ 15.469093] pfeng 46000000.pfe: nxp,fw-class-name: s32g_pfe_class.fw [ 15.469098] pfeng 46000000.pfe: nxp,fw-util-name: s32g_pfe_util.fw [ 15.469151] pfeng 46000000.pfe: netif name: pfe1 [ 15.469158] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:01 [ 15.469166] pfeng 46000000.pfe: netif(pfe1) linked phyif: 1 [ 15.469171] pfeng 46000000.pfe: netif(pfe1) mode: std [ 15.469184] pfeng 46000000.pfe: netif(pfe1) HIFs: count 1 map 02 [ 15.469192] pfeng 46000000.pfe: SGMII AN enabled on EMAC1 [ 15.469196] pfeng 46000000.pfe: EMAC1 PHY less SGMII [ 15.469204] pfeng 46000000.pfe: EMAC1 interface mode: 4 [ 15.469345] pfeng 46000000.pfe: netif name: pfe2 [ 15.469351] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:02 [[ 15.469356] pfeng 46000000.pfe: netif(pfe2) linked phyif: 2 15.469361] pfeng 46000000.pfe: netif(pfe2) mode: std [[ 15.469373] pfeng 46000000.pfe: netif(pfe2) HIFs: count 1 map 04 0[ 15.469380] pfeng 46000000.pfe: SGMII AN enabled on EMAC2 ;[ 15.469384] pfeng 46000000.pfe: EMAC2 PHY less SGMII 3[ 15.469389] pfeng 46000000.pfe: EMAC2 interface mode: 4 2[ 15.469459] pfeng 46000000.pfe: HIF channels mask: 0x0006 m[ 15.469502] pfeng 46000000.pfe: PFE port coherency enabled, mask 0x1e [ 15.469760] pfeng 46000000.pfe: Clocks: sys=300MHz pe=600MHz [ 15.469775] pfeng 46000000.pfe: Interface selected: EMAC0: 0xffffffff EMAC1: 0x4 EMAC2: 0x4 O[ 15.470473] pfeng 46000000.pfe: PFE controller reset done K[ 15.470543] pfeng 46000000.pfe: TX clock on EMAC1 for interface sgmii installed [ 15.470577] pfeng 46000000.pfe: RX clock on EMAC1 for interface sgmii installed [ 15.470629] pfeng 46000000.pfe: TX clock on EMAC2 for interface sgmii installed 15.470662] pfeng 46000000.pfe: RX clock on EMAC2 for interface sgmii installed [[ 15.470842] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34000000 0[ 15.470898] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34080000 m[ 15.470955] pfeng 46000000.pfe: assigned reserved memory node pfebufs@83200000 ][ 15.470982] pfeng 46000000.pfe: assigned reserved memory node pfebufs@835e0000 [ 15.476294] pfeng 46000000.pfe: Firmware: CLASS s32g_pfe_class.fw [45040 bytes] F[ 15.476304] pfeng 46000000.pfe: Firmware: UTIL s32g_pfe_util.fw [23252 bytes] i[ 15.476316] pfeng 46000000.pfe: [pfe_platform_master.c:3629] PFE CBUS p0x46000000 mapped @ v0xffffffc00c000000 (0x1000000 bytes) n[ 15.476324] pfeng 46000000.pfe: [pfe_platform_master.c:3634] HW version 0x101 i[ 15.476332] pfeng 46000000.pfe: [pfe_hw_feature.c:93] Silicon S32G3 s[ 15.476340] pfeng 46000000.pfe: [pfe_platform_master.c:3646] Fail-Stop mode disabled h[ 15.479186] pfeng 46000000.pfe: [pfe_platform_master.c:2783] PFE_ERRORS:Parity instance created e[ 15.479197] pfeng 46000000.pfe: [pfe_platform_master.c:2798] PFE_ERRORS:Watchdog instance created d[ 15.479203] pfeng 46000000.pfe: [pfe_platform_master.c:2814] PFE_ERRORS:Bus Error instance created [ 15.479208] pfeng 46000000.pfe: [pfe_platform_master.c:2827] PFE_ERRORS:FW Fail Stop instance created 15.479214] pfeng 46000000.pfe: [pfe_platform_master.c:2840] PFE_ERRORS:Host Fail Stop instance created 19.535286] pfeng 46000000.pfe: PFE_ERRORS:Fail Stop instance created [0[ 19.535290] pfeng 46000000.pfe: PFE_ERRORS:ECC Err instance created ;[ 19.535300] pfeng 46000000.pfe: BMU1 buffer base: p0xc0000000 1[ 19.535388] pfeng 46000000.pfe: BMU2 buffer base: p0x34000000 (0x80000 bytes) ;[ 19.536682] pfeng 46000000.pfe: register IRQ 76 by name 'PFE BMU IRQ' 3[ 19.536851] pfeng 46000000.pfe: Firmware .elf detected 9[ 19.536853] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x000000002bafc76d). Pool ready. m[ 19.536857] pfeng 46000000.pfe: Uploading CLASS firmware V[ 19.536865] pfeng 46000000.pfe: Selected FW loading OPs to load 8 PEs in parallel A[ 19.536866] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x00000000a2386541). Pool ready. S[ 19.556236] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" T[ 19.571482] pfeng 46000000.pfe: [FW VERSION] 1.8.0, Build: Nov 16 2023, 07:46:11 (nogitaaa), ID: 0x30 [ 19.571773] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0 :[ 19.571814] pfeng 46000000.pfe: Uploading UTIL firmware [ 19.571819] pfeng 46000000.pfe: Selected FW loading OPs to load 1 PEs in parallel I[ 19.574246] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" n[ 19.575323] pfeng 46000000.pfe: FW feature: drv_run_on_g3 i[ 19.575328] pfeng 46000000.pfe: FW feature: jumbo_frames t[ 19.575333] pfeng 46000000.pfe: FW feature: software_vlan_table i[ 19.575337] pfeng 46000000.pfe: FW feature: timestamping a[ 19.575340] pfeng 46000000.pfe: FW feature: qos_mapping l[ 19.575344] pfeng 46000000.pfe: FW feature: core_functionality i[ 19.575348] pfeng 46000000.pfe: FW feature: extended_features z[ 19.575353] pfeng 46000000.pfe: FW feature: flexible_router e[ 19.575357] pfeng 46000000.pfe: FW feature: validate_hif_csum [ 19.575361] pfeng 46000000.pfe: FW feature: err051211_workaround P[ 19.575365] pfeng 46000000.pfe: FW feature: IPsec F[ 19.575368] pfeng 46000000.pfe: FW feature: l2_bridge_aging E[ 19.575373] pfeng 46000000.pfe: FW feature: receive_malformed s[ 19.575379] pfeng 46000000.pfe: FW feature: ptp_conf_check 19.575384] pfeng 46000000.pfe: FW feature: vlan_conf_check [[ 19.575389] pfeng 46000000.pfe: FW feature: hash_load_spread 0[ 19.575395] pfeng 46000000.pfe: FW feature: ingress_vlan m[ 19.575398] pfeng 46000000.pfe: FW feature: safety .[ 19.577825] pfeng 46000000.pfe: VLAN ID incorrect or not set. Using default VLAN ID = 0x01. [ 19.577830] pfeng 46000000.pfe: VLAN stats size incorrect or not set. Using default VLAN stats size =. [ 19.577916] pfeng 46000000.pfe: Software vlan hash table @ p0x20001278 [ 19.578088] pfeng 46000000.pfe: Fall-back bridge domain @ 0x20000a80 (class) [ 19.578092] pfeng 46000000.pfe: Default bridge domain @ 0x20000a78 (class) [ 19.579076] pfeng 46000000.pfe: Routing table created, Hash Table @ p0xc00e0000, Pool @ p0xc00e8000 () [ 19.579290] pfeng 46000000.pfe: Feature err051211_workaround: DISABLED [ 19.587357] pfeng 46000000.pfe: MDIO bus 0 enabled [ 19.593821] pfeng 46000000.pfe: MDIO bus 1 enabled [ 19.599713] pfeng 46000000.pfe: MDIO bus 2 enabled [ 19.599725] pfeng 46000000.pfe: HIF0 not configured, skipped [ 19.600089] pfeng 46000000.pfe: HIF1 enabled [ 19.600319] pfeng 46000000.pfe: HIF2 enabled [ 19.600325] pfeng 46000000.pfe: HIF3 not configured, skipped [ 19.600400] pfeng 46000000.pfe pfe1 (uninitialized): Subscribe to HIF1 [ 19.600407] pfeng 46000000.pfe pfe1 (uninitialized): Host LLTX disabled [ 19.600833] pfeng 46000000.pfe pfe1 (uninitialized): Enable HIF1 [ 19.600994] pfeng 46000000.pfe pfe1 (uninitialized): setting MAC addr: 00:04:9f:be:ef:01 [ 19.601022] pfeng 46000000.pfe pfe1 (uninitialized): PTP HW addend 0x80000000, max_adj configured to b [ 19.601031] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10s 19.535286] pfeng 46000000.pfe: PFE_ERRORS:Fail Stop instance created [0[ 19.535290] pfeng 46000000.pfe: PFE_ERRORS:ECC Err instance created ;[ 19.535300] pfeng 46000000.pfe: BMU1 buffer base: p0xc0000000 1[ 19.535388] pfeng 46000000.pfe: BMU2 buffer base: p0x34000000 (0x80000 bytes) ;[ 19.536682] pfeng 46000000.pfe: register IRQ 76 by name 'PFE BMU IRQ' 3[ 19.536851] pfeng 46000000.pfe: Firmware .elf detected 9[ 19.536853] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x000000002bafc76d). Pool ready. m[ 19.536857] pfeng 46000000.pfe: Uploading CLASS firmware V[ 19.536865] pfeng 46000000.pfe: Selected FW loading OPs to load 8 PEs in parallel A[ 19.536866] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x00000000a2386541). Pool ready. S[ 19.556236] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" T[ 19.571482] pfeng 46000000.pfe: [FW VERSION] 1.8.0, Build: Nov 16 2023, 07:46:11 (nogitaaa), ID: 0x30 [ 19.571773] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0 :[ 19.571814] pfeng 46000000.pfe: Uploading UTIL firmware [ 19.571819] pfeng 46000000.pfe: Selected FW loading OPs to load 1 PEs in parallel I[ 19.574246] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" n[ 19.575323] pfeng 46000000.pfe: FW feature: drv_run_on_g3 i[ 19.575328] pfeng 46000000.pfe: FW feature: jumbo_frames t[ 19.575333] pfeng 46000000.pfe: FW feature: software_vlan_table i[ 19.575337] pfeng 46000000.pfe: FW feature: timestamping a[ 19.575340] pfeng 46000000.pfe: FW feature: qos_mapping l[ 19.575344] pfeng 46000000.pfe: FW feature: core_functionality i[ 19.575348] pfeng 46000000.pfe: FW feature: extended_features z[ 19.575353] pfeng 46000000.pfe: FW feature: flexible_router e[ 19.575357] pfeng 46000000.pfe: FW feature: validate_hif_csum [ 19.575361] pfeng 46000000.pfe: FW feature: err051211_workaround P[ 19.575365] pfeng 46000000.pfe: FW feature: IPsec F[ 19.575368] pfeng 46000000.pfe: FW feature: l2_bridge_aging E[ 19.575373] pfeng 46000000.pfe: FW feature: receive_malformed s[ 19.575379] pfeng 46000000.pfe: FW feature: ptp_conf_check 19.575384] pfeng 46000000.pfe: FW feature: vlan_conf_check [[ 19.575389] pfeng 46000000.pfe: FW feature: hash_load_spread 0[ 19.575395] pfeng 46000000.pfe: FW feature: ingress_vlan m[ 19.575398] pfeng 46000000.pfe: FW feature: safety .[ 19.577825] pfeng 46000000.pfe: VLAN ID incorrect or not set. Using default VLAN ID = 0x01. [ 19.577830] pfeng 46000000.pfe: VLAN stats size incorrect or not set. Using default VLAN stats size =. [ 19.577916] pfeng 46000000.pfe: Software vlan hash table @ p0x20001278 [ 19.578088] pfeng 46000000.pfe: Fall-back bridge domain @ 0x20000a80 (class) [ 19.578092] pfeng 46000000.pfe: Default bridge domain @ 0x20000a78 (class) [ 19.579076] pfeng 46000000.pfe: Routing table created, Hash Table @ p0xc00e0000, Pool @ p0xc00e8000 () [ 19.579290] pfeng 46000000.pfe: Feature err051211_workaround: DISABLED [ 19.587357] pfeng 46000000.pfe: MDIO bus 0 enabled [ 19.593821] pfeng 46000000.pfe: MDIO bus 1 enabled [ 19.599713] pfeng 46000000.pfe: MDIO bus 2 enabled [ 19.599725] pfeng 46000000.pfe: HIF0 not configured, skipped [ 19.600089] pfeng 46000000.pfe: HIF1 enabled [ 19.600319] pfeng 46000000.pfe: HIF2 enabled [ 19.600325] pfeng 46000000.pfe: HIF3 not configured, skipped [ 19.600400] pfeng 46000000.pfe pfe1 (uninitialized): Subscribe to HIF1 [ 19.600407] pfeng 46000000.pfe pfe1 (uninitialized): Host LLTX disabled [ 19.600833] pfeng 46000000.pfe pfe1 (uninitialized): Enable HIF1 [ 19.600994] pfeng 46000000.pfe pfe1 (uninitialized): setting MAC addr: 00:04:9f:be:ef:01 [ 19.601022] pfeng 46000000.pfe pfe1 (uninitialized): PTP HW addend 0x80000000, max_adj configured to b [ 19.601031] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10s 回复：使用具有 3 个接口的 PFEng 驱动程序 @XD我相信该指南是针对 RDB3 硬件的，该硬件在物理上不允许三个 PFE 通过 SGMII 连接。只要芯片本身支持配置，我正在研究的硬件就没有物理限制。 回复：使用具有 3 个接口的 PFEng 驱动程序 我没有对 U-Boot 进行任何修改。由于此消息来自 U-Boot 内的 NXP 代码，您能否确认我应该能够使用此配置？ Serdes0 Lane0 : PCIe Serdes0 Lane1：PFE Serdes1 Lane0：PFE Serdes1 Lane1 : PFE 回复：使用具有 3 个接口的 PFEng 驱动程序 嘿@chenyin_h 是的，这是一块定制板。 我正在使用， Linux - bsp40.0-5.15.145-rt ATF - bsp40.0-2.5 U-Boot - bsp40.0-2022.04 U-Boot hwconfig 是， serdes0:mode=pcie&xpcs1,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G,an=1;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=100;xpcs1_0:speed=1G,an=1;xpcs1_1:speed=1G,an=1 在此设置下，u-boot 也会显示此消息， Failed to configure XPCS0_1 Failed to update XPCS1 for SerDes0 xpcs0_1 and xpcs 1_0 can't be both SGMII SerDes1 configuration will be ignored as it's invalid s32cc_serdes_phy serdes@40480000: Using mode 2 for SerDes subsystem s32cc_serdes_phy serdes@40480000: Unstable RX detected on XPCS1

Dynamically load device tree before U-Boot loads I've been tasked with dynamically selecting a device tree for U-Boot during factory testing. We test various product variants based on NXP i.MX8x, each with different GPIO and peripherals. The PCB variant isn't known to the processor but I need to select the correct device tree before U-Boot loads. I have 3 device tree variants: 1. Base variant for general product startup and Linux boot. 2. Factory tests: variant 1 (inherits from DTS 1). 3. Factory tests: variant 2 (also inherits from DTS 1). I've looked for ways to dynamically choose the device tree for U-Boot but found only methods for Linux (fdt_file/fdt_config). U-Boot's device tree seems fixed in the binary. Ideas to solve this, listed by preference: 1. Use 8 dipswitches on all PCBs to determine the correct device tree and boot to U-Boot console. 2. Select the device tree manually in the U-Boot console then reload the U-Boot console with the new device tree selected. 3. Use UUU to load the correct dtb file during testing. We use NXP's AHAB Secure boot, maybe I'm overlooking something and can load the correct device tree for U-Boot somewhere in AHAB? Thanks for any help, Taylor Re: Dynamically load device tree before U-Boot loads These are very interesting and will probably be very helpful if we get time to revisit this in the future. I've bookmarked both links. Thanks for the help! Re: Dynamically load device tree before U-Boot loads That's what I was expecting. Thanks for verifying. Re: Dynamically load device tree before U-Boot loads https://github.com/nxp-imx/uboot-imx/blob/lf-5.15.71-2.2.2/doc/README.multi-dtb-fit https://github.com/nxp-imx/uboot-imx/blob/lf-5.15.71-2.2.2/dts/Kconfig Re: Dynamically load device tree before U-Boot loads Our default BSP doesn't support the operations and default image is uboot and kernel that are packaged in a CONTAINER.  Regards Harvey

Tearing issue in streaming using IMX RT1170 Hi NXP,             In the RT 1170 EVK with the OV5640 camera 1920 x 1080  is streaming perfectly without any issue but when we use other cameras instead of the default OV5640. We could see tearing issue on the LCD display of the EVK itself. Conditions : 1. Used the SDK example evkmimxrt1170_csi_mipi_yuv_cm7.  2. Streaming cameras other than OV5640 with camera output format YUV422 by changing      the MIPI clock and THs settle values. 3. For lower FPS lesser than 10 I'm not facing any issue but I need to stream 30 FPS. 4. MCUXpresso 11.9.1 and SDK 2.16 Any help regarding this issue would be appreciated. Regards, Ragnar. Re: Tearing issue in streaming using IMX RT1170 Hi @EdwinHz ,                Thanks for the confirmation. Regards, Ragnar. Re: Tearing issue in streaming using IMX RT1170 Hi @Ragnar, I was erroneous on my previous reply. WXGA @60 fps is only possible without rotation and scaling transformations. I apologize for the confusion. BR, Edwin. Re: Tearing issue in streaming using IMX RT1170 Hi @EdwinHz ,          Thanks for the information. Will it support WXGA resolution @60 fps. Even with the rotation and scaling enabled. Regards, Ragnar. Re: Tearing issue in streaming using IMX RT1170 Hi @Ragnar, The RT1170 can support up to WXGA resolution @60 fps. Re: Tearing issue in streaming using IMX RT1170 Hi @EdwinHz ,         I have gone through the i.MX 8/RT MIPI DSI/CSI-2 AN and still I'm facing the same issue. Yes I have tried "csi_mipi_rgb_cm7" here also I'm getting the same issue. The same issue is memtioned in this thread https://community.nxp.com/t5/i-MX-RT/Camera-image-glitching-tearing-when-DEMO-CAMERA-BUFFER-COUNT-3/td-p/1779102. May I know what is the maximum RESOLUTION and FPS that RT1170 supports. Thanks & Regards,      Ragnar. Re: Tearing issue in streaming using IMX RT1170 Hi @Ragnar, Firstly, I would like to recommend you follow the specifications that are described on the following application note: i.MX 8/RT MIPI DSI/CSI-2. Especially the CSI side, since the issue seems to be coming from the different cameras, not the display. What other cameras are you trying? Does this also happen with "csi_mipi_rgb_cm7" example code? BR, Edwin.