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GD3162 Daisy Chain Hi NXP, This is regarding the Daisy Chain configuration of gate drivers in our project. You can refer to the diagram which I've shared for understanding the connections. The chip selects for higher 3 and lower 3 gate drivers are different but the MOSI line going to RH and RL gate drivers is the same MOSI line coming from the micro. Similarly MISO line from BH and BL is connected to the single pin of micro. The issue which I'm facing is, when I'm trying to write the same data to all 6 gate drivers, then I'm succeeding but when I'm trying to configure different data for top 3 and different data for bottom 3 gate drivers in that case data is getting corrupted or wrongly written to some registers. Is it due to the shared MOSI and MISO line? What can be the solution for this issue? Is it possible to configure high and low side gate drivers with separate data? For some registers, it seems to work perfectly but this is not the case for all the registers. Although data is being consistent for higher 3 and lower 3( separately.) Please do respond! Re: GD3162 Daisy Chain Hi NXP,  This is again regarding SPIERR. After configuration of GD registers...I'm not facing SPIERR until PWM is enabled...Once We're enabling PWM to GD in that case SPIERR is triggering sporadically in any of the gate drivers (for 3 phase PMSM motor application). Earlier I phased SPIERR while I was overwriting to the GD registers which was resolved after I gave 50us of delay. But now it triggers only when we enable PWM. Please look to this issue as soon as possible and clarify that whether we need to look into SW or HW Re: GD3162 Daisy Chain Hello Akshat Ooh, sounds great, congratulations. Thank you for letting us know about your implementation, your procedure for solving the SPIERR was interesting. Have a great day and best of luck. Re: GD3162 Daisy Chain Hi Rafar, I did several changes and the issue was resolved: I configured all 6 gate drivers and then I overwrote the required configuration to the lower 3 gate drivers and introduced 100 microseconds of delay after writing each register for all 3 gate drivers. This way I was able to configure lower 3 with a separate configuration and also observed that the SPIERR was resolved. SPIERR was occurring in the previous implementation where I didn't give any delay after writing to one register and I was doing the write operation only for RL and YL gate drivers and not BL (for BL I sent a dummy read frame in Chain). Re: GD3162 Daisy Chain Hi Akshat The AE confirms your connection and gave me several comments for justification and explanation. Yes, your connection looks correct. When using this configuration, only one signal (CSB_L or CSB_H) must be low at once. The frame should contain 24*3 bits per CSB low pulse, containing data for device R/Y/L. There is no issue in sharing MOSI & MISO lines. MISO of gate drivers which have CSB line high will be in high impedance mode, meaning the other daisy-chain will be able to assert MOSI line without any conflict. And any pulses on MOSI/SCLK will be ignored by the gate drivers when CSB is high. The AE insists that you respond to his last request "GD3162 SPIERR." because this information is more detailed to find the problem. “To further debug this issue, as asked previously, please provide waveforms of the complete SPI frame, including INTB line to check when the SPIERR occurs. Please also provide a reference frame where SPI si working (i.e. when you write identical data).” I will be waiting for your response Have a great day and best of luck. Re: GD3162 Daisy Chain Hi Rafar, No the issue is not yet resolved. SPIERR is also occurring when I'm trying to write different data to the lower 3 gate drivers. Please do confirm that in the given design is it really possible to configure all the registers of upper 3 or lower 3 gate drivers separately Re: GD3162 Daisy Chain Hi Akshat I'm working on your other case, "GD3162 SPIERR." I sent you feedback two days ago. Could you please confirm if that issue has been resolved? I've already contacted AE with more experience with this device who is fully available to help us resolve these issues, I just want to confirm if the other issue is resolved so we can continue with this one. I will be waiting for your response Have a great day and best of luck.
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MPC5748G 跨核心共享内存仅在调试中有效 大家好, 我创建了一个项目,它指定了 MPC5748G 开发板的核心 0(Z4_0)和核心 1(Z4_1)闪存中的共享内存部分。 我已配置 LED PA10 和 DS11 来表示核心 0 正常运行。我还配置了 LED PA7 和 DS10 来表示核心 1 正常运行。在调试中,没有问题。 当我终止调试会话并重新连接电路板时,我的项目失败了。 如果我注释掉任何共享内存部分访问,则一切都会在调试或标准模式下正常工作。 我错过了什么?我已将该项目附加到此帖子中。 回复:MPC5748G 跨核心共享内存仅在调试中有效 该代码肯定可以在调试模式下编译和运行。 在“Z4_0 / Sources / shared_mem.c”下rxCAN 被定义为易失性的。为了测试目的,我上次编译时可能注释掉了“rxCAN”。 我已经链接了 Z4_0 编译的 shared_func 和 shared_mem“.o”Z4_1 项目属性下的文件。这是我的机器上的硬编码路径,因此需要针对另一台机器进行更改。 当您引用 main.c 中的代码时,这是针对 Z4_0 还是 Z4_1?如果这会导致混淆,我已将启动顺序首先更改为 Z4_0。
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cannot access terminal FRDM-imx91 Hello, I purchased FRDM-imx91 board. Board was able to boot from eMMC (out of box image) and I can see scripts on terminal, when I try to login as a 'root' terminal does not accept any input from my keyboard. Attached screenshot of terminal. Host- Ubuntu 22.04 Re: cannot access terminal FRDM-imx91 Hey Chavira, HW flow control was off, it solved. Please close the case. Re: cannot access terminal FRDM-imx91 HI @onky! Thank you for contacting NXP Support! I am not able to test now in Linux Host machine, but using windows 11 with teraterm I am not having any issue. Can you try using screen instead of minicom? If it is possible try using windows machine too, to discard any malfunction of the baord. If the problem persists in other machine , please let me know. Best Regards! Chavira
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MPC5748G Shared Memory Accross Core Only Works in Debug Hi All, I've created a project, that specifies a shared memory section in the flash across Core 0 (Z4_0) and Core 1 (Z4_1) of the MPC5748G development board. I've configured LEDs PA10 and DS11 to represent Core 0 running properly. I've also configured LEDs PA7 and DS10 to represent Core 1 running properly. In Debug, there's no issue. When i terminate the debug session and reconnect the board - my project fails. If I comment out any shared memory section access, everything works in debug or standard. What am i missing ? I've attached the project in this post. Re: MPC5748G Shared Memory Accross Core Only Works in Debug Ok, I expected that the elf files are up to date. Anyway, it's caused by missing RAM initialization. Core Z4_0 initializes first 256KB by its startup file: Core Z4_1 initializes  next 256KB: Remaining 256KB is usually initialized by Z2 core which is not present in your project... even if it is defined in project properties: So, you put shared_memory to those last 256KB:  But it's not initialized: If you use debugger in S32DS, it initializes whole RAM explicitly. If you run without debugger, it will crash on bus error when accessing uninitialized RAM. You need to ensure that also this RAM is initialized. Regards, Lukas Re: MPC5748G Shared Memory Accross Core Only Works in Debug This code definitely compiles and runs in debug mode. Under "Z4_0 / Sources / shared_mem.c" rxCAN is defined as volatile. I may of commented out "rxCAN" the last time I compiled, for testing purposes.  I've linked Z4_0's compiled shared_func and shared_mem ".o" files under Z4_1's project properties. This was a hardcoded path on my machine, so will need to be changed for another machine.  When you reference the code in main.c, is this for Z4_0 or Z4_1? I've changed my boot order to Z4_0 first if this is what's causing confusion.  Re: MPC5748G Shared Memory Accross Core Only Works in Debug Hi @EmbeddedS  Was this code really working in debug mode? I just load your elf files to my board (I didn't compile the projects again) and I can see that rxCAN is optimized out and it looks like the code in main.c does not correspond to elf file in the Z4_1 project. Regards, Lukas
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FPU on DSP on the i.MX8MP Hello community, Is there a dedicated FPU on the DSP on the i.MX8M+? The Cadence® Tensilica® HiFi 4 DSP datasheet specifies that the FPU is optional, so is it present in the i.MX8M+ or not? Thanks! Re: FPU on DSP on the i.MX8MP Hello, Yes, the he HiFi 4 Audio Engine consists of three main components: a DSP subsystem, floating point unit, and a subsystem to assist with bit stream access and variable-length (Huffman) encoding and decoding. Best regards.
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关于S32K3 SPI通信速度和数据宽度的问题 大家好, 我正在研究具有 SPI 通信功能的S32K312-Q172设备,我需要执行wakeup_sleep命令,这需要将芯片选择 (CS) 线保持低位约 350 微秒。在我的 Simulink 模型中,我使用 SPI_SetupEB 块(参见第一张图)发送单个 0xFF 的“虚拟字节”。 CS 低持续时间 我如何验证或测量该块是否确实将 CS 线驱动至低电平并持续所需的 350 微秒?有没有推荐的方法来确认使用 SPI_SetupEB 块时 CS 引脚保持低电平的确切时间? DataWidth 与 SpiEbMaxLength 此外,我想在另一种情况下发送 4 个字节的数据。在块参数中,有一个SpiDataWidth字段和一个SpiEbMaxLength字段。我对它们之间的区别感到困惑。例如,如果我想传输4个字节(即32位),是否应该将SpiDataWidth设置为8,并将SpiEbMaxLength设置为32?还是直接将SpiDataWidth设置为32?这两个参数究竟如何相互作用来处理多字节传输? 任何指导都将不胜感激。 非常感谢!
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GD3162 菊花链 你好,恩智浦, 这是关于我们项目中栅极驱动器的菊花链配置。您可以参考我分享的图表来了解其中的连接。高 3 和低 3 栅极驱动器的芯片选择不同,但通向 RH 和 RL 栅极驱动器的 MOSI 线与来自微型的 MOSI 线相同。类似地,来自 BH 和 BL 的 MISO 线连接到微型的单个引脚。我面临的问题是,当我尝试将相同的数据写入所有 6 个栅极驱动器时,我成功了,但是当我尝试为前 3 个栅极驱动器配置不同的数据并为后 3 个栅极驱动器配置不同的数据时,在这种情况下数据会被损坏或错误地写入某些寄存器。这是因为共享 MOSI 和 MISO 线路吗?这个问题有什么解决办法?是否可以使用单独的数据配置高端和低端栅极驱动器?对于某些寄存器来说,它似乎运行完美,但并非所有寄存器都是如此。尽管高 3 和低 3 的数据是一致的(分别)。请回复! 回复:GD3162 菊花链 你好,恩智浦, 这又与 SPIERR 有关。 配置GD寄存器后……直到PWM启用后,我才会遇到SPIERR问题……一旦我们启用PWM到GD,在这种情况下,SPIERR会在任何栅极驱动器中偶尔触发(对于三相PMSM电机应用)。之前,我在覆盖GD寄存器时对SPIERR进行了分阶段处理,在设置了50us的延迟后问题得到了解决。但现在它只有在启用PWM时才会触发。请尽快查看此问题,并明确我们需要检查软件还是硬件。 回复:GD3162 菊花链 你好,阿克沙特 哦,听起来不错,恭喜。 感谢您让我们了解您的实施情况,您解决 SPIERR 的过程很有趣。 祝您度过愉快的一天并好运。 回复:GD3162 菊花链 你好,Rafar, 我做了几处修改,问题得到了解决: 我配置了所有 6 个栅极驱动器,然后将所需的配置覆盖到较低的 3 个栅极驱动器,并在为所有 3 个栅极驱动器写入每个寄存器后引入 100 微秒的延迟。这样,我就能够使用单独的配置来配置较低的 3,并且还观察到 SPIERR 已得到解决。 SPIERR 发生在之前的实现中,其中我在写入一个寄存器后没有给予任何延迟,并且我只对 RL 和 YL 门驱动器而不是 BL 执行写入操作(对于 BL,我在 Chain 中发送了一个虚拟读取帧)。 回复:GD3162 菊花链 你好,Akshat AE 确认了您的连接并向我提供了几条意见以供论证和解释。 是的,您的连接看起来正确。使用此配置时,一次只能有一个信号(CSB_L 或 CSB_H)处于低电平。该帧应包含每个 CSB 低脉冲 24*3 位,包含设备 R/Y/L 的数据。共享 MOSI 和 MISO 线路没有问题。CSB 线为高电平的栅极驱动器的 MISO 将处于高阻抗模式,这意味着其他菊花链将能够毫无冲突地断言 MOSI 线。当 CSB 为高时,栅极驱动器将忽略 MOSI/SCLK 上的任何脉冲。 AE 坚持要求您回应他的最后一个请求“ GD3162 SPIERR ”。因为这些信息更详细,可以找到问题所在。 “为了进一步调试此问题,如前所述,请提供完整 SPI 帧的波形,包括 INTB 线,以检查 SPIERR 何时发生。还请提供 SPI 工作时的参考框架(即当您写入相同的数据时)。” 我将等待你的回复 祝您度过愉快的一天并好运。 回复:GD3162 菊花链 你好,Rafar, 不,问题尚未解决。 当我尝试将不同的数据写入较低的 3 个栅极驱动器时,也会发生 SPIERR。请确认在给定的设计中是否真的可以分别配置上 3 个或下 3 个栅极驱动器的所有寄存器 回复:GD3162 菊花链 你好,Akshat 我正在处理您的另一个案件“ GD3162 SPIERR ”。我两天前就给你发了反馈。您能否确认该问题是否已解决? 我已经联系了对此设备更有经验的 AE,他完全可以帮助我们解决这些问题,我只是想确认其他问题是否已解决,以便我们可以继续解决这个问题。 我将等待你的回复 祝您度过愉快的一天并好运。
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PN7220 Android support Hi, hope you have a good day. I plan to use PN7220 as a pos payment application. Read the datasheet of NFC chip PN7220, the chip supports Android 13-14, I would like to ask whether it can support Android 12? #PN722 #NFC  Re: PN7220 Android support Hello @qiuquanfeng  PN5190 recommends to you, but it cannot be running on Android. Re: PN7220 Android support Hi KellyLi  Thank you very much for your reply! For POS terminal applications, must EMVCo standards be met? Do you have any other chips you recommend? Re: PN7220 Android support Hello @qiuquanfeng  PN7220 support Android onwards 13, if you must start to Android 12 then recomended to switch PN7160.
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imx8-image-full but not need machine learning function features. Hi All, kernel:5.4 evk:imx8mq-evk I can build code by imx8-image-full command, but I not need machine learning fearures. How to remove the Machine Learning features ? or, How to add QT 5 on imx8-image-multimedia build? Re: imx8-image-full but not need machine learning function features. The section <5.6.6 Qt 6 and QtWebEngine browsers> and <5.6.7 NXP eIQ machine learning> from Yocto User Guide can be a reference for such add or remove the required features. Embedded Linux for i.MX Applications Processors | NXP Semiconductors To add QT, a reference can be like, add IMAGE_INSTALL:append = " packagegroup-qt5-imx qtbase" to conf/local.conf Regards Harvey
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S32K344でEth_43_GMAC こんにちは S32K3-T-BOX、MCAL RTD 2.0.0 22_03、Eth_InternalLoopback例、PEマイクロマルチリンクを使用しています。 SCH-50735.pdfに応じて必要なすべてのピンの設定を追加し、ループバックモードを無効にしました。また、サイクリックEth_transmitの遅延を伴うループを追加し、U37 LEDを点滅させて実行を確認しました。 Debug_FLASHすべてが期待どおりに機能し、T-BOXがイーサネットメッセージを周期的に送信すると、T-BOXをオフにしてからオンにすると問題が発生します。LED U37 が点滅してソフトウェアが実行されていることを示しますが、イーサネット メッセージは送信されていません。マルチリンクがデバイスの再起動後には起こらない初期化を行っていることが私には起こりますが、この問題を解決する方法がわかりません。 どなたか解決策をお持ちでしたら、アドバイスをいただければ幸いです。 よろしく ウォン0020 Re:S32K344のEth_43_GMAC どうもありがとうございました、osif遅延は私の問題を解決しました。 Re:S32K344のEth_43_GMAC こんにちは S1がオフになり、LED U36も緑色に点滅します。
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OTAP Using Custom Memory Configuration Results In Erased "INT_STORAGE" and OTAP Failure Hello, Im working on an OTA feature using the internal memory. My custom board has a smaller memory than the KW45B41Z-EVK and as such I need to reconfigure the memory sections. I use the "otap_client_att_bm" demo with only 3 modifications. 1. I changed the gAppOtaExternalStorage_c flag to use the internal memory: 2. I changed the memory partioning, more specifically I reduced the size of "PROGRAM_FLASH": And reduced the size and starting address of the OTAP dump address "INT_STORAGE": Experiment 1:   Experiment 2: I used the following SDK: I conducted all experiments on the evaluation board. My OTA application works fine when using the default location, 0x7a000 for "INT_STORAGE" (memory section for receiving and storing sb3 file). However, when changing the "INT_STORAGE" to a lower address it seems the OTAP process erases the contents of my newly defined "INT_STORAGE" and therby the new sb3 image. To verify this, I modified the "INT_STORAGE" by two sectors, from 0x7a000 to 0x76000, as seen in the image below. Prior to initiating OTAP, the dump address "INT_STORAGE" is empty as seen in the below image. I then initiate the OTAP and set a breakpoint in the "OTA_SetNewImageFlagWithOffset" function, since the image transfer is complete upon entering this function. At this time we can observe that the sb3 image is stored at the new dump address (0x76000), see image below. Once the OTAP sequence is finished, i.e. the device has rebooted it is no longer functional. The memory at the start address explains this.. see image below. The new application is only written up untill address 0xb0. If we look at the new dump address "INT_STORAGE" (0x76000), it too is cleared. However, if we look at the default dump address (0x7a000), it still holds data. Additionally, if we compare the contents of the default "INT_STORAGE" (0x7a000) with the contents of the sb3 file I sent over with an offset of 0x4000, i.e. what was written at address 0x7a000 before the reboot, we can see that it matches up perfectly. This leads me to believe that the first 16kB or 0x4000 bytes of the sb3 image are erased during the reboot of the OTAP process and as such the sb3 file fails to be processed.   I did the same experiment but moved the dump address the other direction, i.e. one sector higher (0x80000). During this experiment the OTA succeeds but the same behavior can be observed in the memory. Default "PROGRAM_FLASH" section is erased, i.e. 0x00 -> 0x7a000. The below screenshots show the memory of the device prior to OTAP initialization, showing that the default "INT_STORAGE" remains unchanged. I then continue to do the same OTAP sequence as previously and break at the same location. At this point the memory at the default "INT_STORAGE" address is identical as prior to the image receival. However, the memory at the new dump address (0x80000) is showing the start of the sb3 file. And the OTAP is successful in booting the new image after the reboot. These two experiments leads me to the conclusion that the erasing of "PROGRAM_FLASH" section does not account for the active memory configuration but rather strictly considers the default memory partioning. Which seems like strange/unwanted behavior as the memory partioning is completly optional. Do you have any fix for the addressing of the erase operation that removes parts of my sb3 image? Or can you provide source code for the OTA bootloader so that I may look into the issue? Re: OTAP Using Custom Memory Configuration Results In Erased "INT_STORAGE" and OTAP Failur Found the issue in the sb3 file generation.. By default the Over The Air Programming tool sets an erase command in the sb3 file from address "0x00" with a size of "0x7a000" effectively erasing parts of the sb3 file stored at "0x76000".  Enabling this line and changing the size to the desired value of "PROGRAM_FLASH" fixed the issue!
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How to use the USB port on MPC5748G? Dear community members:     I used ENET1 on MPC5748G, and used FreeRTOS, and called the socket API to send and receive data. At this time, I also wanted to use USB interface as another way of communication besides the network cable, but after I added the USB module, The Network Interfaces of the tcpip module used by ENET1 have changed from the original tcpip module to usb. Does this mean that the tcpip module of ENET1 cannot be used with the Host CDC (TCPIP) mode of USB? If not, please kindly give me a solution. How do you use USB Device CDC (UART) on MPC5748G if you really can't use both? This approach doesn't seem to see the sample program. MPC5748G-GW-RDB  Re: How to use the USB port on MPC5748G? Thanks for your kindly anwser! Re: How to use the USB port on MPC5748G? If you will program the USB by yourself, there should be no problem with this. Regards, Lukas Re: How to use the USB port on MPC5748G? Thank you very much for your answer. So now I will use pure USB protocol on the board of MPC5748G chip as a Device to communicate with the host, and at the same time use TCPIP ENET1 to communicate. Since the configurator is not suitable, I will not use the Configurator and write the initialization code by myself. Even if the board uses only one core, it's still feasible, right? Re: How to use the USB port on MPC5748G? Hi @H-chips  The stack supports this:  And the configurator strongly requires fatfs or tcpip: Regards, Lukas Re: How to use the USB port on MPC5748G? Hi Lukas Thank you very much for your answer, but I still have a question. If I do not use tcpip or fatfs, can the chip use pure USB protocol to communicate with the Host as a Device? Is it possible to use USB and ENET at the same time? Regards, H-chips Re: How to use the USB port on MPC5748G? Hi @H-chips  I can see that USB requires either fatfs or tcpip component to work. It correspond to this picture: If tcpip with ENET is already used, it can't be obviously used for the USB at the same time (or vice versa, it doesn't matter).  One solution I can see - use second core and second instance of SDK to have two independent tcpip components - one for USB, one for ENET. Regards, Lukas
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LX2160A/LX2080A- DPDK question with PTP function Hi NXP team: When LX2160A/LX2080A initialize DPDK from test.sh script for out application, PTP function can't work. In this condition, can LX2160A can use PTP function? If we want to use PTP, kernel stack and DPDK on single Ethernet port , how to configure DPDK correctly? Please refer to console log below and attachment file.(Initial DPDK script) root@localhost:~# ptp4l -H -s -m -i eth0 --tx_timestamp_timeout=20 -f G.8275.2.cfg ptp4l[87.630]: selected /dev/ptp0 as PTP clock ptp4l[87.630]: port 0: hybrid_e2e only works with E2E ptp4l[87.644]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[87.644]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[92.218]: selected local clock 807871.fffe.12c429 as best master ptp4l[94.052]: port 1: new foreign master 000580.fffe.07f653-5 ptp4l[96.929]: selected local clock 807871.fffe.12c429 as best master ptp4l[98.045]: selected best master clock 000580.fffe.07f653 ptp4l[98.045]: updating UTC offset to 37 ptp4l[98.045]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE ptp4l[101.240]: master offset -1729499211274331771 s0 freq +0 path delay 3189 ptp4l[102.239]: master offset -1729499211274332136 s1 freq -366 path delay 3479 ptp4l[103.237]: master offset -771 s2 freq -1137 path delay 3479 ptp4l[103.237]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[104.236]: master offset 329 s2 freq -268 path delay 3479 ptp4l[105.234]: master offset 659 s2 freq +161 path delay 3326 ptp4l[106.232]: master offset 544 s2 freq +244 path delay 3260 ptp4l[107.231]: master offset 289 s2 freq +152 path delay 3260 ptp4l[108.229]: master offset -12 s2 freq -63 path delay 3326 ptp4l[109.228]: master offset 13 s2 freq -41 path delay 3326 ptp4l[110.226]: master offset -35 s2 freq -85 path delay 3326 ptp4l[111.224]: master offset -381 s2 freq -442 path delay 3769 ^Croot@localhost:~# ls-listni dprc.1/dpni.2 (interface: eth0, end point: dpmac.3) dprc.1/dpni.1 (interface: eth1, end point: dpmac.6) dprc.1/dpni.0 (interface: eth2, end point: dpmac.17) root@localhost:~# ./test.sh + echo dpni.2 + restool dpni destroy dpni.2 dpni.2 is destroyed + export DPDMAI_COUNT=0 + DPDMAI_COUNT=0 + export DPIO_COUNT=8 + DPIO_COUNT=8 + /usr/local/dpdk/dpaa2/dynamic_dpl.sh dpni dpni -b 00:00:00:00:17:00 parent - dprc.1 Creating Non nested DPRC NEW DPRCs dprc.1 dprc.2 Using board type as 2160 Using High Performance Buffers ##################### Container dprc.2 is created #################### Container dprc.2 have following resources :=> * 1 DPMCP * 16 DPBP * 8 DPCON * 16 DPSECI * 2 DPNI * 8 DPIO * 2 DPCI * 0 DPDMAI * 0 DPRTC ######################### Configured Interfaces ######################### Interface Name Endpoint Mac Address ============== ======== ================== dpni.2 UNCONNECTED 00:00:00:00:17:01 dpni.3 UNCONNECTED 00:00:00:00:17:02 + export DPIO_COUNT=8 + DPIO_COUNT=8 + export DPDMAI_COUNT=8 + DPDMAI_COUNT=8 + export DPMCP_COUNT=2 + DPMCP_COUNT=2 + /usr/local/dpdk/dpaa2/dynamic_dpl.sh dpni.3 dpni -b 00:00:00:00:18:00 parent - dprc.1 Creating Non nested DPRC NEW DPRCs dprc.1 dprc.3 dprc.2 Using board type as 2160 Using High Performance Buffers ##################### Container dprc.3 is created #################### Container dprc.3 have following resources :=> * 2 DPMCP * 16 DPBP * 8 DPCON * 16 DPSECI * 2 DPNI * 8 DPIO * 2 DPCI * 8 DPDMAI * 0 DPRTC ######################### Configured Interfaces ######################### Interface Name Endpoint Mac Address ============== ======== ================== dpni.4 dpni.3 00:00:00:00:18:01 dpni.5 UNCONNECTED 00:00:00:00:18:02 + ls-addni --no-link --mac-addr=80:78:71:12:c4:29 Created interface: eth0 (object:dpni.6, endpoint: ) + sleep 2 + echo dprc.2 + restool dpdmux create --default-if=1 --num-ifs=2 --method DPDMUX_METHOD_CUSTOM --manip=DPDMUX_MANIP_NONE --option=DPDMUX_OPT_CLS_MASK_SUPPORT --container=dprc.1 dpdmux.0 is created under dprc.1 + restool dprc connect dprc.1 --endpoint1=dpdmux.0.0 --endpoint2=dpmac.3 + restool dprc connect dprc.1 --endpoint1=dpdmux.0.1 --endpoint2=dpni.6 + restool dprc connect dprc.1 --endpoint1=dpdmux.0.2 --endpoint2=dpni.2 + restool dprc assign dprc.1 --object=dpdmux.0 --child=dprc.2 --plugged=1 + echo dprc.2 root@localhost:~# ptp4l -H -s -m -i eth0 --tx_timestamp_timeout=20 -f G.8275.2.cfg ptp4l[240.582]: selected /dev/ptp0 as PTP clock ptp4l[240.582]: port 0: hybrid_e2e only works with E2E ptp4l[240.601]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[240.604]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[246.375]: selected local clock 807871.fffe.12c429 as best master ptp4l[247.006]: port 1: new foreign master 000580.fffe.07f653-5 ptp4l[250.999]: selected best master clock 000580.fffe.07f653 ptp4l[250.999]: updating UTC offset to 37 ptp4l[250.999]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE ptp4l[254.294]: master offset -863600868970450888 s0 freq -441 path delay 863600868970456647 ptp4l[255.292]: master offset -863600868970450768 s1 freq -321 path delay 863600868970456647 ptp4l[256.291]: master offset -1089 s2 freq -1410 path delay 863600868970456647 ptp4l[256.291]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[257.289]: master offset -431800435712170306 s2 freq -249999999 path delay 1295401304682627354 ptp4l[258.287]: master offset -431800435707937952 s2 freq -249999999 path delay 1295401304682627354 ptp4l[259.286]: master offset -431800435806817514 s2 freq -249999999 path delay 1295401304785740265 ptp4l[260.284]: master offset -431800435905697073 s2 freq -249999999 path delay 1295401304888853177 ^Croot@localhost:~# ls-listni dprc.1/dpni.6 (interface: eth0, end point: dpdmux.0.1) dprc.1/dpni.1 (interface: eth1, end point: dpmac.6) dprc.1/dpni.0 (interface: eth2, end point: dpmac.17) dprc.1/dprc.3/dpni.5 dprc.1/dprc.3/dpni.4 (end point: dpni.3) dprc.1/dprc.2/dpni.3 (end point: dpni.4) dprc.1/dprc.2/dpni.2 (end point: dpdmux.0.2) root@localhost:~# restool -m MC firmware version: 10.36.0 root@localhost:~# uname -r 4.19.90-rt35 Thanks. QorIQ LS2 Device Re: LX2160A/LX2080A- DPDK question with PTP function HI @allenwu622, This is a repsonse  from the specialist team: ---- Why do you require a single interface from MAC? In my understanding , DPDK can't support ptp now, In general we reccomend a HW split solution in order to support ptp with DPDK NXP’s dpdmux is designed to make application not feel multiple interfaces. ---- Re: LX2160A/LX2080A- DPDK question with PTP function Hi @SebastianG : Do you use dpdmux to split the traffic for their case?, I asked you this for the reason that dpdmux can split traffic from single MAC to multiple interfaces. In this case, we should set single mac and single interface on one port. This result can refer to ls-listni result from dpdk_ptp_log.txt. Could you please tell me what kind of packets are required to be processed in dpdk? I mean PTP should use the kernel stack and output the same result in both DPDK and non-DPDK. But the DPDK test result isn't the same as the non-DPDK test result.   Thanks. Re: LX2160A/LX2080A- DPDK question with PTP function Hi @allenwu622, Could you please tell me the following details? Do you use dpdmux to split the traffic for their case?, I asked you this for the reason that dpdmux can split traffic from single MAC to multiple interfaces. Could you please tell me what kind of packets are required to be processed in dpdk? Regards,   Re: LX2160A/LX2080A- DPDK question with PTP function Hi @SebastianG : I have followed your document to test DPDK and PTP. The example used two Ethernet port, I change command to test single Ethernet port for our application request, but the result still fail. how to run dpdk-pkt_split_app on single Ethernet port correctly? More detail refer to attachment file. In this case, LX2160A should been used DPDK and kernel stack for PTP application. But ptp is different test result between DPDK and non-DPDK in same condition, please refer to picture below, PTP seem packets rules change that cause this issue. Thanks. Re: LX2160A/LX2080A- DPDK question with PTP function HI @allenwu622, Talking with a specialist team, you can follow this response: ---- To support PTP with dpdk, we need dpdmux to split traffic: Please refer attached guide to enale dpdmux, PTP traffic can be handled by ethx kernel port. ---- Regards Re: LX2160A/LX2080A- DPDK question with PTP function Hi @SebastianG : Thank you for your support. I am looking forward to your reply. Thanks. Re: LX2160A/LX2080A- DPDK question with PTP function Hi @allenwu622, Sorry for the late response, Just to let you know that I still working on your questions, When I have any update I will let you know Regards Re: LX2160A/LX2080A- DPDK question with PTP function Hi @SebastianG : PTP can work before initialize DPDK from test.sh.  PTP function test LSDK20.04, LSDK2108, LLDP5.15 and LLDP6.1 that can't work correctly with DPDK. Please refer to linker below: https://community.nxp.com/t5/QorIQ/1588-and-DPDK/m-p/1174969/highlight/true we want that single Ethernet port to use PTP from kernel stack and our applications from DPDK. Can LX2160A/LX2080A support above application? How to do it? Or this condition only use PTP from DPDK? Thanks. Re: LX2160A/LX2080A- DPDK question with PTP function Hi @allenwu622, You can run a make config and check the kernel in order to see if the function PTP is enabled, Also you can refer to the sections 7.7.5 and 7.7.6 on the LLDP (https://www.nxp.com/docs/en/user-guide/UG10081_LLDP_6.1.55_2.2.0.pdf) for find commands to verificate the PTP clock. Regards Re: LX2160A/LX2080A- DPDK question with PTP function Hi @SebastianG : Thank you for your support. I am looking forward to your reply. Thanks. Re: LX2160A/LX2080A- DPDK question with PTP function Hi @allenwu622, Just to let you know, that I am working on your questions, when I have any update I will let you know Regards
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Eth_43_GMAC on S32K344 Hello, I use S32K3-T-BOX, MCAL RTD 2.0.0 22_03, Eth_InternalLoopback example and PE micro multilink. I added configuration for all necessary pins according to SCH-50735.pdf and disable Loopback mode. I also added a loop with a delay for cyclic Eth_transmit and flashing the U37 LED to check the run. After Debug_FLASH everything works as expected and the T-BOX sends ethernet message cyclically, the problem occurs after turning the T-BOX off and on. LED U37 flashes to indicate software is running, but the Ethernet message is not being sent. It occurs to me that the multilink is doing some initialization that doesn't happen after the device is restarted, but I don't know how to solve this problem. If anyone has a solution, I would appreciate any advice. Regards won0020 Re: Eth_43_GMAC on S32K344 Thank you very much, osif delay solved my problem. Re: Eth_43_GMAC on S32K344 Hi @won0020 , have you programmed both FLASHs - S32k3 and Flash attached to SJA1110? You also start with the lwip demo - please refer to S32K3 Automotive Telematics Box (T-Box) lwIP Example Guide Training Presentation - refer to slide 15 where small workarounds are described. Best regards, Pavel Re: Eth_43_GMAC on S32K344 Hi, S1 is off, LED U36 also flashes green. Re: Eth_43_GMAC on S32K344 Hi @won0020 , Jumper S1 needs to be set to OFF to enable NVM boot for SJA1110. Best regards, Pavel
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S32K344上的Eth_43_GMAC 你好, 我使用 S32K3-T-BOX、MCAL RTD 2.0.0 22_03、Eth_InternalLoopback 示例和 PE 微多链路。 我根据 SCH-50735.pdf 添加了所有必要引脚的配置并禁用环回模式。我还添加了一个循环,用于循环 Eth_transmit 的延迟并闪烁 U37 LED 来检查运行情况。 Debug_FLASH 之后一切正常,T-BOX 循环发送以太网消息,关闭并打开 T-BOX 后出现问题。LED U37 闪烁表示软件正在运行,但以太网消息未发送。我认为多链路正在进行一些初始化,而这些初始化在设备重启后不会发生,但我不知道如何解决这个问题。 如果有人有解决方案,我将非常感激任何建议。 问候 won0020 回复:S32K344 上的 Eth_43_GMAC 非常感谢,osif延迟解决了我的问题。 回复:S32K344 上的 Eth_43_GMAC 你好, S1关闭,LED U36也闪烁绿色。
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How can I set the MPU for the memory area used by rpmsg? Hi community.   I have using i.MX8MP with yocto kirkstone(5.15.71).   Are the memories used by rpmsg the four listed in the dts file: vdev0vring0, vdev0vring1, vdevbuffer, and rsc_table?   For example, if I refer to https://github.com/nxp-imx/linux-imx/blob/lf-5.15.y/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts, is it correct to assume that it will look like the following?   { /* DDR[0x4000_0000 - 0x8000_0000]: Memory with Normal type, not shareable, non-cacheable */ .RBAR = ARM_MPU_RBAR(3, 0x40000000U), .RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB), }, { /* DDR[0x55000000 - 0x5500FFFF]: Memory with Normal type, SHAREABLE, not cacheable */ .RBAR = ARM_MPU_RBAR(4, 0x55000000), // vdev0vring0: vdev0vring0@55000000, vdev0vring1: vdev0vring1@55008000 .RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_64KB), // for vring. Determine this by referring to the vring item in the dts file. }, { /* DDR[0x550FF000 - 0x550FFFFF]: Memory with Normal type, SHAREABLE, not cacheable */ .RBAR = ARM_MPU_RBAR(5, 0x550ff000), // rsc_table: rsc_table@550ff000 .RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_4KB), // for rsc_table. Determine this by referring to the rsc_table item in the dts file. }, { /* DDR[0x55400000 - 0x54FFFFFF]: Memory with Normal type, SHAREABLE, not cacheable */ .RBAR = ARM_MPU_RBAR(6, 0x55400000), // vdevbuffer: vdevbuffer@55400000 .RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB), // for vdevbuffer. Determine this by referring to the vdevbuffer item in the dts file. },   Best Regards, KASHIWAGI Takashi i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: How can I set the MPU for the memory area used by rpmsg? Hi @Zhiming_Liu san Thank you for reply! For the shared bit in board.c, if we check the function in CMSIS\Core\Include\mpu_armv7.h, the IsShareable is used to control shareable property between multiple bus masters, not two cores. I understand! My question has been resolved. Thank you. Best Regards, KASHIWAGI Takashi Re: How can I set the MPU for the memory area used by rpmsg? Hi The memory can of course be set with more detailed rules. For the shared bit in board.c, if we check the function in CMSIS\Core\Include\mpu_armv7.h, the IsShareable  is used to control shareable property between multiple bus masters, not two cores. /** * MPU Region Attribute and Size Register Value * * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. */ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) Best Regards Zhiming Re: How can I set the MPU for the memory area used by rpmsg? Hi @Zhiming_Liu  san Thank you for reply! Are the memories used by rpmsg the four listed in the dts file: vdev0vring0, vdev0vring1, vdevbuffer, and rsc_table? -->Yes, the related code are like this: Understood. However, this setting allows full access to 0x40000000-0x7FFFFFFF, which is a bit dangerous. It would be easier to understand if the settings for the memory range used by rpmsg were explained in the comments. Also, in sample board.c, Shared Disable is set. The vring, vdevbuffer, and rsc_table areas used by rpmsg are accessed by both the RTOS and Linux. Is it okay not to set the shared bit? Best Regards, KASHIWAGI Takashi Re: How can I set the MPU for the memory area used by rpmsg? Hi Are the memories used by rpmsg the four listed in the dts file: vdev0vring0, vdev0vring1, vdevbuffer, and rsc_table? -->Yes, the related code are like this: rsc_table.c void copyResourceTable(void) { /* * Resource table should be copied to VDEV0_VRING_BASE + RESOURCE_TABLE_OFFSET. * VDEV0_VRING_BASE is temperorily kept for backward compatibility, will be * removed in future release */ memcpy((void *)VDEV0_VRING_BASE, &resources, sizeof(resources)); memcpy((void *)(VDEV0_VRING_BASE + RESOURCE_TABLE_OFFSET), &resources, sizeof(resources)); } board.c /* Region 4 DDR[0x4000_0000 - 0x8000_0000]: Memory with Normal type, not shareable, non-cacheable */ MPU->RBAR = ARM_MPU_RBAR(4, 0x40000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); /* Non-cacheable area is provided in DDR memory, the DDR region [0x80000000 ~ 0x81000000](please see the imx8mp-evk-rpmsg.dts) totally 16MB is revserved for CM7 core. You can put global or static uninitialized variables in NonCacheable section(initialized variables in NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 5 set the address space 0x80000000 ~ 0xBFFFFFFF to be non-cacheable. Then MPU region 6 set the text and data section to be cacheable if the program running on DDR. The cacheable area base address should be multiples of its size in linker file, they can be modified per your needs. */ /* Region 5 DDR[0x8000_0000 - 0xBFFFFFFF]: Memory with Normal type, not shareable, non-cacheable */ MPU->RBAR = ARM_MPU_RBAR(5, 0x80000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); Best Regards Zhiming
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iMXRT1165でSDPを使用したQSPIフラッシュのプログラミング 私は、iMX RT 1165を使用しているカードで生産のためのセットアップを試みています。USB経由のシリアルダウンロードを利用したいのですが。SDKのフラッシュローダーの例を使用し、古いプロセッサ(1060など)でsdphostとblhostを使用するプロセスを説明するいくつかのドキュメントを見つけました。私は、指示は同等であると思っていました。しかし、私はそれを機能させることができませんでした。私はsdphostとblhost用のspsdk pythonツールを使用しています。 それで私の質問はこれらの指示の更新版がありますか?または、これらの指示が同じである場合、私は何が間違っていますか? これが私の試みからの出力です: $ sdphost -v -u 0x1fc9:0x013d write-file 0x20202000 evkmimxrt1160_flashloader_cm7.bin INFO:spsdk.sdp.sdp:Connect: identifier='usb', device=SE Blank RT Family (0x1FC9, 0x013D)path=b'/dev/hidraw1' sn='' INFO:spsdk.sdp.sdp:TX-CMD: WriteFile(address=0x20202000, length=83432) Status (HAB mode) = 2 (0x2) NO DESCRIPTION. Response status = 32 (0x20) NO DESCRIPTION. $ sdphost -v -u 0x1fc9:0x013d jump-address 0x20202400 INFO:spsdk.sdp.sdp:Connect: identifier='usb', device=SE Blank RT Family (0x1FC9, 0x013D)path=b'/dev/hidraw1' sn='' INFO:spsdk.sdp.sdp:TX-CMD: Jump To Address: 0x20202400 INFO:spsdk.sdp.sdp:RX-PACKET: Response: 0x00000020 Status (HAB mode) = 32 (0x20) NO DESCRIPTION. $ blhost -v -u 0x1fc9:0x013d flash-image program.bin erase INFO:spsdk.mboot.mcuboot:Connect: identifier='usb', device=SE Blank RT Family (0x1FC9, 0x013D)path=b'/dev/hidraw1' sn='' INFO:spsdk.mboot.mcuboot:CMD: FlashEraseRegion(address=0x00000000, length=90112, mem_id=0) INFO:spsdk.mboot.mcuboot:CMD: Status: 10000 (0x2710) Unknown Command. Response status = 10000 (0x2710) Unknown Command.
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NTAG 424 DNA can still be erased even if locked? Hi, I want to use NTAG 424 DNA tags to include in products, with a URL to access additional details. I'd like to lock these tags so they can't be changed or erased by anyone after shipping. I tried the lock features in the NXP TagWriter Android app, both "Soft protection" and "Lock tag". Both of these were effective in preventing writing different data to the tags. However, I can still use the "Erase to factory default" feature to wipe the content. After this, the tags appear as having "empty" content, and since they're locked I can't write on them again, so they effectively became useless. Is there a different way to lock them so they can't be erased? Maybe with different software? BTW, I also tried to use "Password protection" to protect writing these tags, but I kept getting an error that the feature is not supported by these tags. I'm attaching the output of TagInfo when scanning a tag that was first soft protected and then erased and is now un-writable. Thanks, any insights would be appreciated. Re: NTAG 424 DNA can still be erased even if locked? Great, that worked for recovering those tags, thanks for the reply. Sounds like the fact that the locking command in the writer app might either have a bug or is incorrectly worded. Anyway, I'll try out the app you linked to. Thanks, Daniel Re: NTAG 424 DNA can still be erased even if locked? Hello @dgobera, Good Day! Thank you very much for your interest in our products. For being able to write again to the "erased to factory default" tags, you may try using the ''Remove protection'' feature of the NXP TagWriter app, this has worked for me when replicating the procedure you described, after that you should be able to write an NDEF to the tag again. For preventing the tag from being overwritten or erased, the write access right of the NDEF file within the tag must be changed, this procedure is described in section 8.2.3.3 and 11.7 of the NTAG 424 DNA Data Sheet. In order to perform this procedure, I would suggest having a look at our recommended RFIDDiscover Software application, which is a tool that is meant to be used with the PEGODA Contactless Smart Card Reader And offers an easy way of exploring the NTAG 424 DNA and other smart cards' features. Please consider that in order to have access to the tool you would need to sign an NDA since this software is part of NXP's secure resources. My best regards, Daniel.
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USB CDC ACM (Serial) SDK middlewere: DCD (Carrier) update of host Hello, I am trying to understand how I update the host when carrier is updated. As far as I can see the host gets the last value from `kUSB_DeviceCdcEventSetControlLineState` from `acmInfo->uartState` if `~USB_DEVICE_CDC_UART_STATE_RX_CARRIER` is unset. When device looses carrier and wish to update the host, how is this done? I guess there should be some notification, but I could not find how to initiate this notification in the SDK. I am using `SDK_25_03_00_MIMXRT1171xxxxx`. Thank you Alon Re: USB CDC ACM (Serial) SDK middlewere: DCD (Carrier) update of host Thank you @Gavin_Jia for the hint! I successfully manage to update the host and reuse the callback logic using the following code: void update_host(void) { if (s_usbCdcAcmInfo.dtePresent) { usb_device_cdc_acm_request_param_struct_t param = { .setupValue = s_usbCdcAcmInfo.dteStatus, .interfaceIndex = ((usb_device_cdc_acm_struct_t *)s_UsbInterface4XXXCicVcom.cdcAcmHandle)->interfaceNumber, }; USB_DeviceInterface4XXXCicVcomCallback(s_UsbInterface4XXXCicVcom.cdcAcmHandle, kUSB_DeviceCdcEventSetControlLineState, &param); } } Explanation for future reference: 1. The device can send serial state notifications at any time using the CIC vcom input endpoint. 2. The host can query status, this is triggered by kUSB_DeviceCdcEventSetControlLineState, as response (1) is sent. 3. kUSB_DeviceCdcEventSerialStateNotif is triggered after notification was sent. Re: USB CDC ACM (Serial) SDK middlewere: DCD (Carrier) update of host Hello @Gavin_Jia , Thank you so much for assisting. I cannot find how to use the callback when I have an event in the device side. The scenario is the device loses connectivity and requires to notify the host which is pulling dcd signal in a loop. When the host pulls dcd, I cannot see callback being called. I saw the `kUSB_DeviceCdcEventSerialStateNotif` but as this is event at the device side, I do not understand how to trigger the host in order to update state. Let's say I call `USB_DeviceCdcAcmEvent(,kUSB_DeviceCdcEventSerialStateNotif,)` what do I do in the callback? I guess I need to send some packet to host, but not via `USB_DeviceCdcAcmSend` as this sends regular data. Regards, Re: USB CDC ACM (Serial) SDK middlewere: DCD (Carrier) update of host Hi @alonbl , Sorry for the misunderstanding of kUSB_DeviceCdcEventSerialStateNotif in my previous reply: This event is the signal from the USB stack that informs you that sending is complete after the call to USB_DeviceCdcAcmSend has completed successfully. The CDC ACM driver on the host polls the interrupt IN endpoint. After the device has sent a new serial state notification via USB_DeviceCdcAcmSend, the next poll of the host takes this notification and updates what it considers to be the state of the serial port . And it is possible to send notifications usingUSB_DeviceCdcAcmSend, the key is the difference in the second parameter, the bulk IN endpoint is used to transmit packets and the interrupt IN endpoint is used to transmit status information or control notifications. But the key point remains that you need to write your own logic and serial State buffer in the application. Hope it helps! Best regards, Gavin       Re: USB CDC ACM (Serial) SDK middlewere: DCD (Carrier) update of host Hi @alonbl , Thanks for your interest in NXP MIMXRT series! Using the USB_DeviceCdcVcomCallback() function in virtual_com.c in the SDK as an example, I don't think it accomplishes the scenario you describe. It may be necessary to consider calling USB_DeviceCdcAcmSend() for this scenario. Best regards, Gavin
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How to burn PF1510 A0 version? How to burn after configuring OTP for PF1510 A0 version? I don't see the burning board on the official website, but there is GUI software Re: How to burn PF1510 A0 version? Or leave a phone number Re: How to burn PF1510 A0 version? PInout is a little different, but they all belong to the same series and can share this programming board Re: How to burn PF1510 A0 version? So can PF1510 be programmed with PF1550 programmer? I checked the documentation and found that the PIN pins and GUI are slightly different. Re: PF1510 A0版本怎么烧录? Hi Michael 选择PF1550的program board 里面有usermanual客户参考怎么使用: KITPF1550FRDMPGM - PF1550 programming socket board | NXP Semiconductors
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