LAN96455F Ethernet Switch Integration with i.MX95 – Device Tree Guidance Hi NXP team, We're integrating a Microchip LAN96455F Ethernet switch (LAN9645x family) onto a custom i.MX95 19x19 LPDDR5 board (based on imx95-19x19-evk.dts), and would appreciate guidance on the correct device tree integration Re: LAN96455F Ethernet Switch Integration with i.MX95 – Device Tree Guidance For Linux, model the LAN96455F as a DSA Ethernet switch if you expect Linux to expose/manage the external switch ports individually. The i.MX95 ENETC/NETC Ethernet MAC that connects to the switch’s CPU/uplink port should be the DSA conduit interface; the LAN96455F ports become DSA user netdevs. DSA is designed for switches with a dedicated CPU port connected to an SoC Ethernet controller, and it creates per-front-panel “user” interfaces rather than a separate netdev for the CPU port itself .
A good device-tree shape is:
/* Replace &enetX / &mdioX with the actual i.MX95 BSP labels used
* in imx95-19x19-evk.dts / imx95.dtsi for your selected NETC ENETC port.
*/
/* i.MX95 ENETC port connected to LAN96455F CPU/uplink port */
&enetX {
status = "okay";
/* Must match the electrical interface between i.MX95 and LAN96455F:
* "rgmii-id", "rgmii", "sgmii", "2500base-x", etc.
*/
phy-mode = "rgmii-id";
/* MAC-to-switch CPU port is normally PHY-less, so describe it
* as a fixed link unless the LAN96455F CPU port is actually
* managed through a PHY/PCS.
*/
fixed-link {
speed = <1000>;
full-duplex;
};
};
/* MDIO controller used to access the switch management interface.
* i.MX95 NETC has an external master MDIO interface for external PHYs,
* supporting Clause 22 and Clause 45 .
*/
&mdioX {
status = "okay";
ethernet-switch@0 {
/* Use the compatible string from the LAN9645x driver/binding
* shipped in your kernel/BSP. Do not invent this string.
*/
compatible = "microchip, ";
reg = <0>; /* MDIO address strapped on the board */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
/* If this external port has an external PHY:
* phy-handle = <&phy0>;
* phy-mode = "...";
*/
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
/* LAN96455F CPU/uplink port number must match the
* Microchip datasheet/driver definition.
*/
port@N {
reg = ;
label = "cpu";
ethernet = <&enetX>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
Key points to check before finalizing the DTS:
Use the actual LAN9645x binding from your kernel. I could not confirm a public mainline LAN96455F-specific binding from the retrieved sources, so the compatible string above is intentionally a placeholder. Check your NXP BSP/Microchip driver tree under Documentation/devicetree/bindings/net/dsa/ or the Microchip LAN9645x driver source.
Put ethernet = <&enetX>; on the switch CPU port, not on every switch port. The DSA port binding says the ethernet property is a phandle to the host Ethernet device that the switch port is connected to.
CPU/DSA ports need a phylink-style link description. For a CPU port with ethernet = <&enetX>; , the binding requires phy-mode and one of fixed-link , phy-handle , or managed .
Use fixed-link for a direct MAC-to-switch CPU-port connection. The common Ethernet binding defines fixed-link with speed , full-duplex , and optional pause properties; supported fixed-link speeds include 10/100/1000/2500/5000/10000 Mbit/s in the object form.
Be precise with RGMII delay mode. phy-mode = "rgmii-id" means the PCB does not provide the RGMII clock/data delay and the MAC/PHY side must provide internal delay; plain "rgmii" means the PCB routing provides the delay. For most custom boards, "rgmii-id" is the expected starting point unless your layout deliberately adds the delay.
Do not also configure the i.MX95 MAC as if it had a normal external PHY if the MAC is connected to the switch CPU port. In the DSA model, the MAC is the conduit, and the external user ports are represented by the switch port nodes.
Expect Linux interfaces such as lan0 , lan1 , etc. DSA creates user network devices for front-panel ports, and the DSA label property becomes the netdev name.
Bring-up checks:
dmesg | grep -i -E "dsa|lan964|mdio|enetc|netc"
ip link
cat /sys/class/net/ /dsa/tagging 2>/dev/null
ip link set up
ip link set lan0 up
ethtool lan0
If no lanX interfaces appear, debug in this order: MDIO address/strap value, reset GPIO timing, interrupt GPIO if required by the driver, correct LAN9645x compatible , correct CPU-port reg , and correct phy-mode /fixed-link speed between i.MX95 and the switch.
Use the i.MX95 ENETC port as the DSA conduit, describe the LAN96455F under the MDIO/SPI management bus with a ports block, and make the switch CPU port point back to the ENETC MAC using ethernet = <&enetX> plus a valid phy-mode and fixed-link / managed / phy-handle .
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