CAN FD bus off state S32k146 Hi, We need to implement a CAN FD communication with 1Mb/s as bitrate. Unfortunately it's not working. The data would be written correct in the RAM, but in Canoe there is no message incomming. I've attached the ESR1, the CAN_init and a function to send a message. Hope you can help me. Sandra Re: CAN FD bus off state S32k146 Hi Petr, thx for your reply. We tested the FlexCAN example, but with the same failures. We detect, that our controller has some issues with the soldering pads. Best regards Sandra Re: CAN FD bus off state S32k146 Hi, seems you are detecting bit errors during transmission which leads to entering bus off state and recovering and so on. A cause of bit error detection can be various, most often inactive CAN transceiver, incorrect bit rate setting, etc.  It would be great to measure TX/RX and CAN line with scope-analyzer to see real signal as well. For your code, seems you have wrong setting for CBT register. I can recommend to use below tool which helps you with calculation https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/MPC5xxx-S32Kxx-LPCxxxx-CAN-CAN-FD-bit-timing-calculation/ta-p/1119319 BR, Petr

S32k310 RTDs port on TCM memories Hi There, I would run some deterministic Functions on TCM, and by consecuence some RTDs (ADC, PWM,...). I noticed, in *Memmap.h files,  that mcal_* linker sections  are spread in few linker sections; for example some sections are cacheable other non  canheable and other unknown sections. I read the RTD IM and UM manuals but there is no info about TCM topic Is there some documentation to port RTDs memory section on I/D TCMs ? NB Also, in s321k310 there is 16kb of SRAM and 64k od DTCM, so an efficient  and accurate partiting of data memory  mapping is almost necessary in any case. Best Regards Fabio  Best Regards Fabio Re: S32k310 RTDs port on TCM memories Hi@FabioG Please refer to the attachment.

I2C MPC5478G こんにちは、MPC5748Gを使ってアンプと通信したいです。パワー・アーキテクチャーのi2c_transfer_mpc5748gのサンプルコードを使っています。アンプのアドレスは0x70です。これを実現するにはどのような変更が必要ですか？また、 i2Cドライバーはアドレス-> データを送信しますが、私はそれをアンプ（アドレス）-> アンプレジスタ（サブアドレス）-> データのアドレスにしたいです。

i.MXRT1176 SAI1 Data channels 2,3,4 & fifo combine Hi there.  I'm trying to use as many SAI data pins as possible on the RT1176.  I am aware that for SAI 1 data channels 2, 3, and 4, the Tx and Rx data lines share a pin, and so can only be assigned to Tx or Rx. Lets try and use all 3 of them all for Tx anyway.. So my configuration is  SAI 1 pins: - Tx1 - Rx1 - Tx2 - Tx3 - Tx4 Using the config tool, I do this on the 'playback' tab Then I generate the code and run, but I hit an assert in fsl_sai_edma.c: #if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE /* Allow multi-channel transfer only if FIFO Combine mode is enabled */ assert( (saiConfig->channelNums <= 1U) || ((saiConfig->channelNums > 1U) && ((saiConfig->fifo.fifoCombine == kSAI_FifoCombineModeEnabledOnWrite) || (saiConfig->fifo.fifoCombine == kSAI_FifoCombineModeEnabledOnReadWrite)))); #endif   This suggests that you MUST use fifo combine if you use more than 1 SAI data channel. The manual states (p.3475): Combining FIFOs for transmit data channels allows one data channel to use the FIFOs of all enabled channel FIFOs, with identical data output on each enabled data channel. Combining FIFOs for receive data channels allows one data channel to use the FIFOs of all enabled channel FIFOs, with received data from channel 0 stored into each enabled data channel. This suggest that if using SAI 1 data pin2, 3, or 4 for Tx, they will all just output the same data as on pin1?! And if using them for Rx... well it doesn't say but it sounds like pins 2,3 and 4 will be ignored? Can you please clarify this or point me to some more detailed documentation?  Are SAI1 data pins 2,3,4 independently usable at all?   Many thanks. Re: i.MXRT1176 SAI1 Data channels 2,3,4 & fifo combine Thanks for the reply, I tested this today and it appears to work as described. It would be really useful to have this functionality detailed in the SAI FIFO combine section of the RT1176 ref manual because it currently reads as though it is not possible to have different data on different SAI 1 pins. Many thanks Re: i.MXRT1176 SAI1 Data channels 2,3,4 & fifo combine Hello @mttjcksn, I highly recommend consulting this application note, where the multi-channel functionality is explained in greater detail. Additionally, the FCOMB register indicates the following: This means that the FIFO will store data for each enabled channel. Also, if you exprience any issue, do not hesitate to let me know. BR Habib

LSDK21.08 LS1043AQDS SETUP Hello, Wang. With your help, my board ls1043aqds has entered uboot. I use LSDK 21.08 for development, and the boot mode is TF-A. But my qspi flash is small, only 16MB, so I can't write itb directly to flash and start kernel and ramdisk from qspi. I think the next priority is to burn the kernel and ramdisk into 16GB emmc, and then load the kernel from emmc. But I don't know if I have to use an external writer to burn emmc at the moment, and I don't know exactly what needs to be modified and compiled in the next work. I really hope to get your help and look forward to your reply as soon as possible. thank you. @yipingwang Re: LSDK21.08 LS1043AQDS SETUP Dear WANG,Thank you very much for your help, I can now enter the official ubuntu file system. Re: LSDK21.08 LS1043AQDS SETUP You need to modify LS1043AQDS device tree according to your custom board. In LSDK 21.08 build environment: $ source setup.env $ flex-builder -c linux -m ls1043aqds Go to Linux Kernel source code components/linux/linux, please modify arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts according to your custom board. For example, please delete the following device node, if there is no IFC NOR flash on your custom board. nor@0,0 { compatible = "cfi-flash"; reg = <0x0 0x0 0x8000000>; big-endian; bank-width = <2>; device-width = <1>; }; Then rebuild Linux Kernel $ flex-builder -c linux -m ls1043aqds Regenerate itb image $ flex-builder -i mkitb -r yocto:tiny Get the image flexbuild_lsdk2108_github/build/images/lsdk2108_yocto_tiny_LS_arm64.itb If you need to the bootpartition image, please regenerate it with the following command $ flex-builder -i mkbootpartition -a arm64 Re: LSDK21.08 LS1043AQDS SETUP Wang,Thank you very much for your technical reply, and I am honored to get your help in debugging this series of boards for the first time. I have made some progress following your suggestions, but it seems that the kernel is stuck and cannot continue. I have attached the log, and I hope to get your help on what I should do next so that I can successfully enter ramdisk. @yipingwang  Re: LSDK21.08 LS1043AQDS SETUP The emmc device is not removable, you could copy all your images to the USB device, then boot up the target board with image lsdk2108_yocto_tiny_LS_arm64.itb and deploy Ubuntu rootfs to emmc device in Linux on the target board. For example under u-boot, => ext2load usb 0:1 0xa0000000 lsdk2108_yocto_tiny_LS_arm64.itb => bootm 0xa0000000#ls1043aqds Under Linux on the target board, please run the following commands to deploy Kernel and Ubuntu rootfs to emmc device. $ flex-installer -i pf -d /dev/mmcblk0 $ flex-installer -b boot_LS_arm64_lts_5.10.tgz -r rootfs_lsdk2108_ubuntu_main_arm64.tgz -d /dev/mmcblk0 Note:/dev/mmcblk0 is the emmc device name on the target board.

How qemu load dtb on LS2088ardb I'm buiding images for LS2088ardb by using Yocto command "bitbake fsl-image-networking" Now I load the dtb in the QEMU but can't boot into kernel and step by step SOP as below:  Open 2 terminals in my host PC (Ubuntu 20.04)  Use the command to run QEMU in first terminal: $ qemu-system-aarch64 \   -smp 8 \   -machine type=virt,gic-version=3 \   -m 2048 \   -cpu cortex-a72 \   -kernel Image \   -serial tcp::4446,server,telnet \   -drive if=none,file=fsl-image-networking-ls2088ardb.rootfs-20240711074828.ext4,id=foo,format=raw \   -device virtio-blk-device,drive=foo \   -append 'root=/dev/vda rw console=ttyAMA0,115200 rootwait earlyprintk' \   -monitor stdio Output as below QEMU 4.2.1 monitor - type 'help' for more information (qemu) qemu-system-aarch64: -serial tcp::4446,server,telnet: info: QEMU waiting for connection on: disconnected:telnet:0.0.0.0:4446,server Use the command to connect QEMU in second terminal: telnet 0.0.0.0 4446 I can success to boot into kernel Trying 0.0.0.0... Connected to 0.0.0.0. Escape character is '^]'. [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd083] [ 0.000000] Linux version 6.6.23-gb586a521770e (oe-user@oe-host) (aarch64-fsl-linux-gcc (GCC) 13.2.0, GNU ld (GNU Binutils) 2.42.0.20240216) #1 SMP PREEMPT Fri Jun 7 13:15:57 UTC 2024 [ 0.000000] KASLR disabled due to lack of seed [ 0.000000] Machine model: linux,dummy-virt ... ... ls2088ardb login: root root@ls2088ardb:~# Trying to use the command to load device tree in first terminal $ qemu-system-aarch64 \ -smp 8 \ -machine type=virt,gic-version=3 \ -m 2048 \ -cpu cortex-a72 \ -kernel Image \ -serial tcp::4446,server,telnet \ -dtb fsl-ls2088a-rdb.dtb \ -drive if=none,file=fsl-image-networking-ls2088ardb.rootfs-20240711074828.ext4,id=foo,format=raw \ -device virtio-blk-device,drive=foo \ -append 'root=/dev/vda rw console=ttyAMA0,115200 rootwait earlyprintk' \ -monitor stdio Output as below QEMU 4.2.1 monitor - type 'help' for more information (qemu) qemu-system-aarch64: -serial tcp::4446,server,telnet: info: QEMU waiting for connection on: disconnected:telnet:0.0.0.0:4446,server Use the command to connect QEMU in second terminal Trying 0.0.0.0... Connected to 0.0.0.0. Escape character is '^]'. It stay here and can't boot into kernel I try to add debug info and step same as Step4-5 -d int,cpu_reset Output  CPU Reset (CPU 0) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 1) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 2) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 3) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 4) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 5) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 6) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 7) R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 PSR=40000000 -Z-- A usr26 CPU Reset (CPU 0) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 1) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 2) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 3) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 4) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 5) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 6) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h CPU Reset (CPU 7) PC=0000000000000000 X00=0000000000000000 X01=0000000000000000 X02=0000000000000000 X03=0000000000000000 X04=0000000000000000 X05=0000000000000000 X06=0000000000000000 X07=0000000000000000 X08=0000000000000000 X09=0000000000000000 X10=0000000000000000 X11=0000000000000000 X12=0000000000000000 X13=0000000000000000 X14=0000000000000000 X15=0000000000000000 X16=0000000000000000 X17=0000000000000000 X18=0000000000000000 X19=0000000000000000 X20=0000000000000000 X21=0000000000000000 X22=0000000000000000 X23=0000000000000000 X24=0000000000000000 X25=0000000000000000 X26=0000000000000000 X27=0000000000000000 X28=0000000000000000 X29=0000000000000000 X30=0000000000000000 SP=0000000000000000 PSTATE=400003c5 -Z-- EL1h Exception return from AArch64 EL1 to AArch64 EL1 PC 0x423790d0 Taking exception 1 [Undefined Instruction] ...from EL1 to EL1 ...with ESR 0x0/0x2000000 ...with ELR 0xffff800080027b20 ...to EL1 PC 0xffff800080011200 PSTATE 0x3c5 Here is my build image folder boot_ls2088ardb_lts_6.6.tgz core-image-minimal-ls2088ardb.rootfs-20240711074828.cpio.gz core-image-minimal-ls2088ardb.rootfs-20240711074828.cpio.gz.u-boot core-image-minimal-ls2088ardb.rootfs-20240711074828.manifest core-image-minimal-ls2088ardb.rootfs-20240711074828.spdx.tar.zst core-image-minimal-ls2088ardb.rootfs-20240711074828.tar.gz core-image-minimal-ls2088ardb.rootfs-20240711074828.testdata.json core-image-minimal-ls2088ardb.rootfs.cpio.gz->core-image-minimal-ls2088ardb.rootfs-20240711074828.cpio.gz core-image-minimal-ls2088ardb.rootfs.cpio.gz.u-boot->core-image-minimal-ls2088ardb.rootfs-20240711074828.cpio.gz.u-boot core-image-minimal-ls2088ardb.rootfs.manifest->core-image-minimal-ls2088ardb.rootfs-20240711074828.manifest core-image-minimal-ls2088ardb.rootfs.spdx.tar.zst->core-image-minimal-ls2088ardb.rootfs-20240711074828.spdx.tar.zst core-image-minimal-ls2088ardb.rootfs.tar.gz->core-image-minimal-ls2088ardb.rootfs-20240711074828.tar.gz core-image-minimal-ls2088ardb.rootfs.testdata.json->core-image-minimal-ls2088ardb.rootfs-20240711074828.testdata.json fitImage->fitImage--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fitImage--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fitImage-core-image-minimal-ls2088ardb.rootfs--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fitImage-core-image-minimal-ls2088ardb.rootfs-ls2088ardb->fitImage-core-image-minimal-ls2088ardb.rootfs--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fitImage-its--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.its fitImage-its-core-image-minimal-ls2088ardb.rootfs--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.its fitImage-its-core-image-minimal-ls2088ardb.rootfs-ls2088ardb->fitImage-its-core-image-minimal-ls2088ardb.rootfs--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.its fitImage-its-ls2088ardb->fitImage-its--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.its fitImage-linux.bin--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fitImage-linux.bin-ls2088ardb->fitImage-linux.bin--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fitImage-ls2088ardb.bin->fitImage--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin fsl-image-networking-ls2088ardb.rootfs-20240711074828.cpio.gz fsl-image-networking-ls2088ardb.rootfs-20240711074828.cpio.gz.u-boot fsl-image-networking-ls2088ardb.rootfs-20240711074828.ext4 fsl-image-networking-ls2088ardb.rootfs-20240711074828.manifest fsl-image-networking-ls2088ardb.rootfs-20240711074828.spdx.tar.zst fsl-image-networking-ls2088ardb.rootfs-20240711074828.tar.gz fsl-image-networking-ls2088ardb.rootfs-20240711074828.testdata.json fsl-image-networking-ls2088ardb.rootfs.cpio.gz->fsl-image-networking-ls2088ardb.rootfs-20240711074828.cpio.gz fsl-image-networking-ls2088ardb.rootfs.cpio.gz.u-boot->fsl-image-networking-ls2088ardb.rootfs-20240711074828.cpio.gz.u-boot fsl-image-networking-ls2088ardb.rootfs.ext4->fsl-image-networking-ls2088ardb.rootfs-20240711074828.ext4 fsl-image-networking-ls2088ardb.rootfs.manifest->fsl-image-networking-ls2088ardb.rootfs-20240711074828.manifest fsl-image-networking-ls2088ardb.rootfs.spdx.tar.zst->fsl-image-networking-ls2088ardb.rootfs-20240711074828.spdx.tar.zst fsl-image-networking-ls2088ardb.rootfs.tar.gz->fsl-image-networking-ls2088ardb.rootfs-20240711074828.tar.gz fsl-image-networking-ls2088ardb.rootfs.testdata.json->fsl-image-networking-ls2088ardb.rootfs-20240711074828.testdata.json fsl-ls2088a-qds--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.dtb->fsl-ls2088a-qds.dtb fsl-ls2088a-qds.dtb fsl-ls2088a-qds-ls2088ardb.dtb->fsl-ls2088a-qds.dtb fsl-ls2088a-rdb--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.dtb->fsl-ls2088a-rdb.dtb fsl-ls2088a-rdb.dtb fsl-ls2088a-rdb-ls2088ardb.dtb->fsl-ls2088a-rdb.dtb Image->Image--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin Image--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin Image-ls2088ardb.bin->Image--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.bin ls2088ardb_boot.scr modules--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.tgz modules-ls2088ardb.tgz->modules--6.6.23+git0+b586a52177-r0-ls2088ardb-20240711074828.tgz u-boot.bin->u-boot-tfa-2024.04++fslgit-r0.bin u-boot.bin-tfa->u-boot-tfa-2024.04++fslgit-r0.bin u-boot.bin-tfa-secure-boot->u-boot-tfa-secure-boot-2024.04++fslgit-r0.bin u-boot-ls2088ardb.bin->u-boot-tfa-2024.04++fslgit-r0.bin u-boot-ls2088ardb.bin-tfa->u-boot-tfa-2024.04++fslgit-r0.bin u-boot-ls2088ardb.bin-tfa-secure-boot->u-boot-tfa-secure-boot-2024.04++fslgit-r0.bin u-boot-qoriq-initial-env-ls2088ardb-tfa->u-boot-qoriq-initial-env-ls2088ardb-tfa-2024.04++fslgit-r0 u-boot-qoriq-initial-env-ls2088ardb-tfa-2024.04++fslgit-r0 u-boot-qoriq-initial-env-ls2088ardb-tfa-secure-boot->u-boot-qoriq-initial-env-ls2088ardb-tfa-secure-boot-2024.04++fslgit-r0 u-boot-qoriq-initial-env-ls2088ardb-tfa-secure-boot-2024.04++fslgit-r0 u-boot-qoriq-initial-env-tfa->u-boot-qoriq-initial-env-ls2088ardb-tfa-2024.04++fslgit-r0 u-boot-qoriq-initial-env-tfa-secure-boot->u-boot-qoriq-initial-env-ls2088ardb-tfa-secure-boot-2024.04++fslgit-r0 u-boot-tfa-2024.04++fslgit-r0.bin u-boot-tfa-secure-boot-2024.04++fslgit-r0.bin Thanks Re: How qemu load dtb on LS2088ardb You cannot emulate the device in a PC. This would need to create a new QEMU image that works with all the modules of the LS2088A and we do not have any image like that. What I understood was to simulate an Arm OS with QEMU in the board and you can for sure do that.

I2C接口的MPC5478G 你好，我想使用 MPC5748G 与放大器通信。我正在使用 Power Architecture 的 i2c_transfer_mpc5748g 示例代码。放大器的地址是0x70。我需要做哪些修改才能实现这一点？此外，i2c 驱动程序发送 地址->数据，但我想使其成为放大器的地址（地址）->放大器寄存器（子地址）->数据。

I2C MPC5478G Hi, I want to communicate with an amplifier using the MPC5748G. I'm using the i2c_transfer_mpc5748g sample code from the Power Architecture. The amplifier's address is 0x70. What modifications do I need to make to achieve this? also i2c driver sends adress->data  but i want to make it adress of amplifier(adress) ->amplifier register(subadress)-> data. Re: I2C MPC5478G Hi, the Slave device address is set within Component inspector and it is automatically sent as first byte after START is issued. The Slave’s register/memory address, must be stored into first byte(s) of the “txBuffer” depending on address size.   So assuming 16bit address is used and you want to write 8 bytes (1,2,3,..,8) to Slave address 0x000C, then prepare txBuffer as   txBuffer = {0x00, 0x0C, 1, 2, 3, 4, 5, 6, 7, 8};   and use I2C_DRV_MasterSendDataBlocking(instance, txBuffer, 10, true, timeout);   If you want to read 8 bytes from the same memory address then use this   I2C_DRV_MasterSendDataBlocking(instance, txBuffer, 2, false, timeout); // just memory/register address will be sent after Slave address so total 3 bytes, STOP is not generated I2C_DRV_MasterReceiveDataBlocking(instance, rxBuffer, 8, true, timeout); // Repeat Start is issued following Slave address and waiting reading for 8 bytes Hope it helps. BR, Petr

FRDM-MCXN947 : smartdma_camera_flexio_mculcd demo example issue : only one line on LCD Hello, I successfully solder and connect my FRDM-MCXN947 to OV7670 camera and LCD PAR-LCD-S035 since I am able to run the demo "Multiple face detection on MCXN947" provided using MCUXpresso Projects from Application Code Hub.  My problem is that I encounter the following issue executing the "frdmmcxn947_smartdma_camera_flexio_mculcd example" : only one line of the camera is displayed on the top of the LCD display. I am running the latest MCUXpresso version (24.12) I get the "frdmmcxn947_smartdma_camera_flexio_mculcd example" directly from MCUXpresso using "Welcome"->Import SDK Examples ->Go straight to the Wizard" then frdmmcxn947 board (SDK 2.x_MCXN947/version 2.16.100/Manifest 3.14.00), then "display_examples" then "smartdma_camera_flexio_mculcd".  This project compiles, download and executes correctly but I get a black lcd screen with only one line updated by the camera. I read the doc given on AN14191.pdf ( on https://docs.nxp.com/bundle/AN14191/page/topics/software.html#topic_30f829c2-0650-45e1-ab55-320979025292__fig_xmg_lpv_c1c" ) but that doesn't help much to understand the poorly commented code of the example. Many thanks for your help, Thierry MCXN Re: FRDM-MCXN947 : smartdma_camera_flexio_mculcd demo example issue : only one line on LCD Dear Alice, Thank you so much, it works now : the problem was the source code example : I used the one provided from the MCUxpresso interface (Import SDK Examples ->Go straight to the Wizard" then frdmmcxn947 board (SDK 2.x_MCXN947/version 2.16.100/Manifest 3.14.00), then "display_examples" then "smartdma_camera_flexio_mculcd") which is faulty. The AN14191SW.zip  is perfect ! (and totaly different). Have a nice day ! Re: FRDM-MCXN947 : smartdma_camera_flexio_mculcd demo example issue : only one line on LCD Hello @tgrandpi  Please download the code from the AN14191 resource https://www.nxp.com/docs/en/application-note-software/AN14191SW.zip .  I've tested it on my end, it works well. Thank you. BR Alice Re: FRDM-MCXN947 : smartdma_camera_flexio_mculcd demo example issue : only one line on LCD Thank you Alice, but I already did that 3 modifications in order to run successfully the "Multiple face detection"  demo. So this is not a hardware problem since that demo work. Thank you for your help. Re: FRDM-MCXN947 : smartdma_camera_flexio_mculcd demo example issue : only one line on LCD Hello @tgrandpi  Please rework your board according to the following picture: BR Alice

S32K311-寄存器无法访问 大家好， 我最近从 S32K312 切换到 S32K311 统一引导加载程序，但我遇到了一些驱动程序寄存器不再可访问的问题。具体来说，我正在使用 CAN 通信，某些寄存器（SFR）似乎无法访问。我附上了一张图片来说明这个问题。 有人能提供关于这个问题的潜在原因或解决方案的见解吗？如能就 S32K312 和 S32K311 之间的配置差异（可能影响寄存器（SFR）访问）提出任何建议，我们将不胜感激。 提前谢谢！ 顺祝商祺！

S32K311 - Register Can not Access Hi all, I recently switched from the S32K312 to the S32K311 Unified Bootloader, but I am encountering an issue where some of the driver registers are no longer accessible. Specifically, I am using CAN communication, and certain registers (SFRs) seem to be unreachable. I’ve attached an image to illustrate the issue. Could anyone provide insights into potential causes or solutions for this problem? Any advice on configuration differences between the S32K312 and S32K311 that could be affecting register (SFRs) access would be greatly appreciated. Thank you in advance! Best regards. Re: S32K311 - Register Can not Access Hi The S32K3XXRM mentions: The peripherals working on the system clock should be clock-gated used the MC_ME.PRTNx_COFBy_CLKEN configurations. According to Table 260. MC_ME partition peripheral mapping and clock control, please check the value of FlexCAN 0: PRTN1_COFB2_CLKEN[REQ65] If this bit was 0, Please check whether the FlexCAN 0 clock gate is enabled in the S32 Configuration Tool. Also, does your program call the Clock_Ip_Init function? Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

S32K311-登録にアクセスできません 皆さん、こんにちは 最近、S32K312からS32K311ユニファイドブートローダーに切り替えましたが、一部のドライバーレジスターにアクセスできなくなるという問題が発生しています。具体的には、CAN通信を使用していますが、特定のレジスタ（SFR）にアクセスできないようです。問題を説明する画像を添付しました。 この問題の潜在的な原因や解決策についての洞察を誰かが提供できますか？レジスタ（SFR）へのアクセスに影響する可能性のあるS32K312とS32K311の設定の違いに関するアドバイスをいただければ幸いです。 お手数ですが、よろしくお願いいたします。 よろしくお願いいたします。

How to suppress a specific compiler warning message CW 11.1 Hi, I'm using CW 11.1 because my processor is MC9S08DZ60A. I am porting some code from another compiler. I would like to suppress compiler warning C1420, return value ignored, because it flags every printf. I found a screen that looks likely, but I put C1420 in there, and also tried just 1420, and the warnings still come up. See attached screenshot. Is there a way to stop a specific warning message number, or a list of them? Thanks, Lloyd Re: How to suppress a specific compiler warning message CW 11.1 Thank you so much! That worked! Then I added more on the same line like this: -WmsgSd1420 -WmsgSd2705 I appreciate the help! Lloyd Re: How to suppress a specific compiler warning message CW 11.1 Hi @lslonim  Please add  -WmsgSd1420 to compiler setting to disable C1420 Thanks, Jun Zhang

NCJ29D5の安全なNVストレージエリアにあるキーをTrace32で削除できますか？ こんにちは、皆さん。 私はUCJ29D5を使ってUWBレンジングを行っています。 キーをNVエリアに保存することに成功しましたが、trace32を使ってキーを消去する方法はありますか？ 'FLASH.ERASE'コマンドで試してみましたが、失敗しました。 メモリ領域は保護領域だと思いますが、何か方法を知りたいです。 ありがとうございます。

我可以通过 Trace32 删除 NCJ29D5 安全 NV 存储区域中的密钥吗？ 大家好， 我正在使用 NCJ29D5 进行 UWB 测距。 我成功地将密钥存储到 NV 区域，但是有没有办法使用 trace32 擦除它？ 当我尝试使用“FLASH.ERASE”命令时，失败了。 我认为内存区域是安全区域，但我想知道任何方法。 谢谢。

Can I delete a key in the secure NV storage area of NCJ29D5 by Trace32? Hi All, I'm working with NCJ29D5 for UWB ranging. I succeed to store a key into NV area, but is there any way to erase it using the trace32? When I tried it with 'FLASH.ERASE' command, i failed. I think the memory area is secured area, but I want to know any method. Thanks. Re: Can I delete a key in the secure NV storage area of NCJ29D5 by Trace32? Hello, Hope you are doing well. Sorry for the inconvenience this might cause you but as the information of this product it's under NDA (Non-Disclosure Agreement) the information it's not public. For more information about the chip could you please contact one of our distributors available in the Distributor Network|NXP? Or if you have any direct contact who helped you getting this device, please contact them. Regards, Ricardo

S32G2 LLCE payload features Hello, i know that LLCE can filter specific CAN IDs which supports host offloading. i want to know if there is any ways we can filter certain payload in LLCE.    For example, drops the frame if ID = 0x20 and first byte of payload = 0x00 Re: S32G2 LLCE payload features hi，chansookang Thank you for contacting us. I know what you mean. I think you can operate the payload in software. LLCEAF cannot recognize the messages inside LLCE. If you want to do so, you can purchase FDK and modify the LLCE code. In addition, refer to the LLCE_firmware_user_guide, no payload manipulation is implemented (e.g. payload split). BR Joey

使用ldf文件配置s32k116 我有一个主节点，它可以发送 2 个帧 ID 为 0x30 的信号，并且想将 s32116 evb 配置为从属节点。 就我而言，当我发送帧 ID 为 0x30 的信号时，结果为 0x01 0xff 0xff 0xff。任何一个 gpio 引脚都应该为高电平（led 应该发光）或者当发送帧 ID 为 0x30 的信号（即 0x00 0xff 0xff 0xff）时，配置了 led 的相同 gpio 应该变为低电平。 非常感谢与此相关的任何建议或简单示例。 提前致谢！ 谢谢与问候， 桑托什

ldfファイルを使用したs32k116の設定 フレームID 0x30の2つの信号を送信できるマスターノードがあり、s32116 evbをスレーブノードとして設定したいと考えています。 私の場合、フレームIDが0x30の信号を0x01 0xff 0xff 0xffとして送信すると。GPIOピンのいずれかがHigh（LEDが光るはずです）か、フレームIDが0x30の0x00 0xff 0xff 0xffの信号が送信されると、LEDで構成された同じGPIOがローになるはずです。 これに関連する提案や簡単な例は大歓迎です。 前もって感謝します！ ありがとう & よろしく、サントッシュ

rt1170 MIPI DSIはビデオモードを使用してDCSコマンドを送信します こんにちは、 私は現在、rt1170評価キットでST7703I TFTモバイルシングルチップドライバーに対応しようとしています。ST7703Iはビデオモードのみをサポートしており、DCSコマンドはビデオモードを使用して送信する必要があります。 MIPI DSIドライバー ( https://mcuxpresso.nxp.com/api_doc/dev/2207/a00014.html) には、" dsi_SetdpiConfigでビデオモードを開始できると書かれています。 "DSI_SetDpiConfig () を呼び出した後、" dsi_TransferBlocking () " という関数が付いたDSCコマンドは、ビデオモードで転送されますか？