******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 146 * (voltage level of VDD) to check core voltage level and displays it into * terminal window. No external connection required excluding terminal via eSCI. * * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Example configures Sigma_Delta ADC and periodically converts ANA0_SDA0 input * (EVB's potentiometer can be connected i.e. J53-1 --> PO15) and displays * results in the terminal window (USBtoUART bridge J21). Terminal settings is * 19200-8-no parity-1 stop bit-no flow control on eSCI_A. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *                  eSCI_A is USBtoUART bridge (connector J21) * EVB connection:  For ADC: J53-1 (EVB pot's wiper) --> PO15 (header P22) * ********************************************************************************

A requirement of the standard is to detect the accumulation of latent defects. To meet this requirement the MPC5744P has the ability to execute Built-In Self-Test (BIST) procedures.

******************************************************************************** * Detailed Description: * This example shows how to reprogram the shadow flash. * * It is highly recommended to read application note "Preventing Device Lockout * via Censorship on MPC55xx and MPC563x Families" * http://www.freescale.com/files/32bit/doc/app_note/AN3787.pdf * * This examples erases the shadow flash, then it restores censorship information * and then NVUSRO nonvolatile register is reprogrammed to disable the watchdog. * The watchdog is disabled by clearing of bit WATCHDOG_EN in NVUSRO. It ensures * that watchdog is disabled automatically during startup of MCU. * Watchdog can be also disabled by software (shown in the code). * * It is important to execute the code from RAM memory because Read-While-Write * is not supported here. * * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC560B 144LQFP, SPC5604B, silicon mask set 2M27V * Target :  internal_FLASH, RAM * ********************************************************************************

******************************************************************************** * Detailed Description: * DRUN mode with max core frequency(200MHz) generated from PPL0 * This example demonstrates ECC error injection to peripheral RAM *  and ECC error reporting to MEMU * --------------------------------------------------------------------------------------------- * Test HW:  MPC57xx * Maskset:  1N15P * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference *           ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version 1.1    Aug-15-2017     b21190(Vlna Peter)  EIM ECC RAM error injection to DMA added *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * ------------------------------------------------------------------------------ * Test HW:        XPC5607B 176LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             PPC5607BMLUAM03Y * Fsys:             64/48 MHz * Debugger:      Lauterbach Trace32 *                      PeMicro USB-ML-PPCNEXUS * Target:           RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows how to use CRC module. * - CRC32 is used * - byte stream is written into input register * - one test case uses direct access to CRC registers * - second test case uses DMA to write the data stream * - the results can be compared using this online calculator: *   http://www.zorc.breitbandkatze.de/crc.html * - screenshots from online calculator are attached * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH ********************************************************************************

This is simple example of the usage of Flash Array Integrity Check (FAIC) function that is available on all MPC56xx devices.   The FAIC reads data from selected and unlocked flash blocks and calculates the MISR signature. User can compare the MISR signature calculated by flash controller (in runtime) with MISR calculated by offline tool (this is done during development, not in runtime) from s-record file. If the MISR is identical, we know that the content of selected flash blocks corresponds to content in s-record file and that there are no ECC errors (single bit or double bit ECC errors).

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON) * by initialization of instruction cache and enabling of branch prediction. * Example suppose MCU is configured for LSM (Lock-step mode). * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH, RAM * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC564AKIT324S it initializes EBI for mounted external SRAM. * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, third LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * Second core is started and second LED blinking is being performed by it. * The example configures the device for maximum performance (OPTIMIZATIONS_ON) * by initialization of instruction cache and enabling of branch prediction. * Example suppose MCU is configured for DPM (Decoupled-parallel mode). * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH, RAM * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * IT INITIALIZES EBI FOR EXTERNAL SRAM CONNECTED TO XPC564AKIT324S AND TEST IT. * * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT324S * MCU:            SPC5644AMVZ1 0M14X QAK1235G * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * * The example shows how to initialize 3 submodules to generate 120° phase shift * between submodules. * CNTR register of each submodule is initialized with shifted value when PWM * generators are disabled using FORCE feature. * * ------------------------------------------------------------------------------ * Test HW:  MPC5744P (MPC5744P-257DS + MPC577xx motherboard) * Maskset:  1N15P * Target :  internal_FLASH, RAM * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * P8.13    - A[12] .. FlexPWM A[2] output * P8.14    - A[13] .. FlexPWM B[2] output * P10.8    - C[7] .. FlexPWM A[1] output * P10.7    - C[6] .. FlexPWM B[1] output * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC564AKIT324S it initializes EBI for mounted external SRAM. * Its intention is to offer advanced startup code additional to CW stationery. * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************   NOTE: It cannot be used with MPC5642A device, only with MPC5644A and MPC5643A !   For MPC5642A device, use following project instead of attached one: Example XPC5642AKIT PinToggleStationery CW10.6

******************************************************************************** * Detailed Description: * Application performs basic initialization then it initializes EBI for external * SRAM connected to MPC5777C-516DS and test it by write and read of block of * data. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 3N45H * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  jumper J4 on position 1-2 (choosing CS0) *                  EMIOS1 (PortI P16-0) --> USER_LED_1 (P7-1) to see LED blink ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.1  Jun-26-2017  David Tosenovjan  Initial version 0.2  Oct-13-2017  David Tosenovjan  Lower CLKOUT frequency 0.3  Feb-02-2020  David Tosenovjan  Corrected External_SRAM_MMU_init                                     Ported to S32 design studio *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts and NMI for * WKPCFG pin (GPIO213). * User needs to connect ETPUC9 pin to user switch and general purpose output * ETPUA30 to user LED 1: * ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * WKPCFG  (PortC P10-4)  --> USER_SWITCHES (P6-4) * Jumper J523 position 1-2 needs to be OPEN! * * If rising edge is detected (i.e. button is pressed), machine check exception * is triggered and LED1 on is toggled. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  WKPCFG  (PortC P10-4)  --> USER_SWITCHES (P6-4) *                  Jumper J523 position 1-2 needs to be OPEN! ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.0  May-22-2019  David Tosenovjan  Initial version                            *******************************************************************************/

******************************************************************************** * Detailed Description: * * Configures the FlexCAN to transmit and receive a CAN message. * ECC reporting in the FlexCAN module is disabled. * * In this config, CAN_A transmits a message. CAN_B receives the message. * CAN_A MB8 is configured to send data. CAN_A sends message each 1sec. * This interval is generated by PIT. * CAN_B MB9 is configured to receive a message, SW polling is used. * * Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * * ------------------------------------------------------------------------------ * Test HW:        XPC563MKIT * MCU:            PPC5633MMLQ80 * Fsys:           80/60/40/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** Detailed Description: Example shows configuration of SIUL External interrupts using SDK driver. EIRQ0 (PA3) and EIRQ11 (PE12) are configured for detecting rising edge. Those pins are connected to switches SW1 and SW2 on DEVKIT board. EIRQ1 (PA6) is configured for detecting falling edge. Within its interrupt routines a LEDs are toggled upon edge detecting. See PinSetting component for pins configuration within "Routing" and "Functionals Properties" tabs. To see falling edge on PA6 just connect pin (J2.1) to GND shortly. * ------------------------------------------------------------------------------ * Test HW:         DEVKIT-MPC5748G * MCU:             PPC5748GSMKU6 0N78S * Target:          Debug_FLASH * EVB connection: * Compiler:        S32DS.POWER.2017.R1 * SDK release:     S32_SDK_S32PA_BETA_2.9.0 * Debugger:        S32DS, Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date        Author       Description of Changes 0.1 Jun-13-2019 Petr Stancik Initial version *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start both Z7 cores, interrupts initialization, blinking three LED by interrupts, * initializes and display notice via UART terminal and then terminal ECHO. * Each core serves one interrupt and one LED. * * The example configures the device for maximum performance by initialization of * instruction/data cache and enabling of branch prediction for each core * (startup.s files). * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz *                    Both Z7 Cores 266MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  USER LED1 connected to P19.0, LED2 connected to P19.5 *                  LED3 connected to P19.8 *                  For correct UART functionality connect: *                  J14.2 to P12.6 *                  J13.2 to P12.7 * ********************************************************************************