******************************************************************************** * Detailed Description: * Enable external interrupt on pin PA[3]. * If falling edge is detected, interrupt is triggered and LED1 on PE[4] is * toggled. * * Connect external signal to PA[3] or connect push button by wire. * * ------------------------------------------------------------------------------ * Test HW:  TRK-MPC5606B, SPC5606B 0N32E * Target :  internal_FLASH, RAM * Fsys:     64 MHz PLL with 8 MHz crystal reference * ********************************************************************************

This config tool simplifies PLL setting calculation and clock configuration for MPC5777C device. Version 1.3 added option to select between 264/300 MHz MCU versions.                 Follow these steps                 Note: Macros have to be enabled!                 1. Enter frequency of used XOSC and desired PLL0 and PLL1 output.      - put values into cells B14, Q13 and Q20 of the "Clocks" sheet      - check if it is Valid or Invalid      - "PLLconfig" sheet shows possible PLLs configurations                   2. Configure System and AUX clock selectors and its Dividers      - check calculated frequency of System/Peripheral clocks      - if Invalid change source clock and Divider value to keep Max freq                 3. Copy generated code by pressing "Copy Code" button

******************************************************************************** * Detailed Description: * * Purpose of the example is to show how to intentionally generate FCCU fault * causing reset either directly or by FOSU (simulating by non-handled FCCU * fault). Example configures FCCU, then an error is injected with using of * Noncritical Fault Fake register and after re-booting reset cause is evaluated. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates frequency modulation at 20kHz with 250 steps. * System frequency which is modulated is 40MHz. * ------------------------------------------------------------------------------ * Test HW:   MPC57xx EVB + MPC5748G minimodule * Maskset:   1N81M * Target :     SRAM * Fsys:        40 MHz PLL * ******************************************************************************** Revision History: 1.0     Oct-29-2014     b21190(Vlna Peter)  Initial Version 1.1    Nov-20-2014    b21190(Vlna Peter)  Modified for Cut2.0 1.2    Nov-20-2014    b21190(Vlna Peter)  Added SWT_0 dissabling in startup 1.3    Mar-10-2016    b21190(Vlna Peter)  Fixed clock configuraion for PLL 1.4    Jun-30-2017    b21190(Vlna Peter)  Added 20kHz frequency modulation *******************************************************************************/ Measure modulated system Frequency at PG[7] - SYSCLK0 pin.

******************************************************************************** * Detailed Description: * Example of core watchdog implementation on Cobra 55. It executes on core 0 * All the functions are in the file "watchdog.c" *WatchDogCreate(delay, FirstTimeout, SecondTimeout) -> create/configure the wathdog timer *WatchDogStart() -> start the watchdog timer *WatchDogService() -> acknowledge the watchdog timer * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-416DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi bit ECC error in * internal SRAM or FLASH (user can choose it in the option at the end of main * function) and how to handle this error with respect to constraints given by * MPC5675K architecture (ECSM/RGM/FCCU relation and ECC error handling through * reset). The example is only possible to run in internal_FLASH target. Power- * -on-reset is required after downloading the code into MCU's flash. The example * displays notices in the terminal window (setting specified below). No other * external connection is required. * Example also shows impact of enabled cache (macro OPTIMIZATIONS_ON). * * ------------------------------------------------------------------------------ * Test HW:        MPC5675KEVB * MCU:            PPC5675KFMMSJ in Lock-Step mode * Fsys:           180/150 MHz CORE_CLK * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

This excel tool helps to configure MMU on e200z cores. It generates asm code and also command for Lauterbach debugger for selected configuration of TLB entry.

******************************************************************************** * Detailed Description: * * * This example demonstrate functionality of XBIC_1 error injection *  capability. The fault is generated on DMA transfer to SRAM. *  After fault generation it is propagated to FCCU unit as NCF[59]. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * ********************************************************************************

******************************************************************************** * Detailed Description: * DRUN with PLL 160MHz active. * Example of INTC configuration. PIT timer is triggering an * interrupt which is served in PIT ISR. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N06M * Target :  Internal Flash * Fsys:     160 MHz PLL * ******************************************************************************** Revision History: 1.0     Oct-29-2014     b21190(Vlna Peter)  Initial Version 1.1    Nov-20-2014    b21190(Vlna Peter)  Modified for Cut2.0 1.2    Apr-23-2015    b21190(Vlna Peter)  Added INTC driver and PIT ISR 1.3    May-14-2015    b21190(Vlna Peter)  Dissabling SWT in Startup code 1.4     Jun-06-2017    b21190(Vlna Peter)  ported for MPC5746C *******************************************************************************/

This document shows, how to use CRC gen utility in CodeWarrior for MCU IDE.   1) Create new project in CodeWarrior. 2) Create a file calc_crc.crc in the Project/Project_Settings/Linker_File directory. 3) Open project settings, choose C/C++ Build ->Settings and add the following command to Post-build steps: "${MCU_TOOLS_HOME}/bin/crcgen.exe" "${BuildLocation}/${BuildArtifactFileName}" -crc "${ProjDirPath}/Project_Settings/Linker_Files/calc_crc.crc" -srec "${BuildLocation}/${BuildArtifactFileName}.crc.mot" 26   4) Open calc_crc.crc and configure required parameters. Meaning of single lines is described in CodeWarrior reference manual called Targeting_Microcontrollers I used following code (it is only example)   5) Build your project. 6) File MPC5604B-CRCTest.elf.crc.mot was created   Now you have s-record, which contains CRC and which could be loaded to microcontroller.

******************************************************************************** * Detailed Description: * * This example shows usage of FlexPWM to generate independent * PWM signals from Submodule0. The PWMX output is set for 50% duty. * PWMA/PWMB outputs vary its duty cycles. * The DMA module is used to reload VAL2-5 registers. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * P11.10 - D[9] .. FlexPWM X[0] output * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows how to use SPI module in extended SPI mode * - DSPI3 is configured as a master * - SPI1 is configured as a slave * - Frame size is configured to 32bit * - Two writes are necessary to load one 32bit frame to TX FIFO * - For more details about the timing settings see application note AN4830 * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH ********************************************************************************

******************************************************************************** * Detailed Description: * Example demostrates MCU behaviour when single bit RAM ECC error occurs by * intentional ECC error injection. * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, starts second core * initializes and display notice via UART terminal and then terminals ECHO. * * * Test HW:              MPC5688EVB * MCU:                   SPC5668GMMG 0N61C * Terminal:              19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:                   116 MHz * Debugger:             Lauterbach Trace32 *                             PeMicro USB-ML-PPCNEXUS * Target:                  RAM, internal_FLASH * EVB connection:   User LED 4 connected to pin P28-10 * *

******************************************************************************** * Detailed Description: * This example demonstrates PMC SW triggered self-test configuration and execution * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N15P and 0N15P * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference *            ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version 1.1     Apr-20-2017     b21190(Vlna Peter)  added software PMC self-test *******************************************************************************/

How to get latest MCAL HF version from your NXP website account if you have already registered and applied MCAL SW package.   Access www.nxp.com, login with your account            

* Owner:            b21190(Vlna Peter) * Version:          1.0 * Date:               May-09-2018 * Classification:   General Business Information * Brief:                 BIST demonstration *                    ******************************************************************************** * Test HW:  MPC57xx * Maskset:  3N23A * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0       Oct-22-2014     b21190(Vlna Peter)  Initial Version 1.1        Mar-19-2015        b21190(Vlna Peter)  Added ADC_0 driver 1.2        Mar-19-2015        b21190(Vlna Peter)  Added STCU self-test for core1 *******************************************************************************/

******************************************************************************** * Detailed Description: * This example demonstrates how to configure CGM )clock generation module) * and supply by clock all main peripherals. * Example demonstrate FCCU fake fault injection for fault 15. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx EVB + MPC5777M minimodule * Maskset:  0N50N * Target :  internal_FLASH * Fsys:     200 MHz PLL * ******************************************************************************** Revision History: 1.0     Nov-04-2014     b21190(Vlna Peter)  Initial Version 1.1     Feb-04-2016     b21190(Vlna Peter)  Fixed Clock configuration 1.2    Feb-06-2017    b21190(Vlna Peter)  FCCU fake fault injection *******************************************************************************/

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. This is defined by BRS macro. * Baudrate during arbitration phase is set to 500kbps, during data phase 1Mpbs * because of PHY used on the EVB. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, ISR is used to read new message. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. * * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.D + MPC57xx MOTHER BOARD Rev.C * MCU: SPC5777CCMM03 3N45H * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************