This config tool simplifies PLL setting calculation and clock configuration for MPC5744P device.                  Follow these steps                  Note: Macros have to be enabled!                  1. Enter frequency of used XOSC and desired PLL0 and PLL1 output.                 - put values into cells B11, Q10 and Q17 of the "Clocks" sheet                 - check if it is Valid or Invalid                 - "PLLconfig" sheet shows possible PLLs configurations                  2. Configure System and AUX clock selectors and its Dividers                 - check calculated frequency of System/Peripheral clocks                 - if Invalid change source clock and Divider value to keep Max freq                    3. Copy generated code by pressing "Copy Code" button

******************************************************************************** * Detailed Description: * * * This example shows synchronization between FlexPWM, CTU and ADC modules. * The FlexPWM Submodule 0 is initialized to generate PWM signal, and rising edge * of PWM B0 signal is used to generate trigger signal for CTU module. The CTU module * sends two commands to ADCs. Single conversion mode is used, so ADC0 ch0 and ch1 * are sampled. The conversion result is used to modify PWM B0 rising egde position * and change delay between external trigger and ADC sequence triggering. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P8.1  - A[0]  .. GPIO output, used to see CTU-ADC ISR period * P9.1     - B[7]  .. ADC0 AN[0] input * P9.2     - B[8]  .. ADC0 AN[1] input * P16.4 - I[3] .. CTU0 EXT TRG output   * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * * connect Trimmer J53.1 to P9.1 to change position of PWM B0 rising edge * connect Trimmer J53.1 to P9.2 to change CTU trigger delay from PWM B0 rising edge * * see CTU0 EXT TRG output signal (toggle on each trigger) on P16.4 with respect of PWM signals * ********************************************************************************

This document describes the configuration, restrictions, principles and correct usage of FCCU module implemented on MPC5744P device. This document is preliminary release.

The aim of the MPC5643L PWM triggered measurement concept is to introduce hardware  subsystem concept of autonomous triggering of ADC measurement by PWM module in desired time intervals and automatic storing of measured data into buffer located in SRAM. This autonomous measurement concept will offload the microprocessor’s core and presents the very precise way how to achieve the ADC time critical measurement synchronized with PWM signal generated by FlexPWM module.

******************************************************************************** * Detailed Description: * * LINFlex UART TXFIFO transmit using DMA * LINFlex UART mode with FIFO receive using DMA * * * EVB connection: * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * See results on PC terminal (baudrate 19200, Data bits 8, Stop bits 1, Parity none). * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH (debug mode, release mode without debugging information) * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows possible implementation of frequency and duty cycle * measurement with the help of eMIOS module. * Two eMIOS channels are used and set to IPWM and IPM modes. The first channel * measures the positive pulse width and the second channel measures the period. * * EVB connection: * PJ7.5 to PJ7.6 ... connect external pulse signal to this * * See result on PC terminal (9600, 8N1) * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC564xB/C, SPC5646C 0N32E silicon * Target :  internal_FLASH, RAM * Fsys:     120 MHz PLL0 * Debugger: Lauterbach Trace32. script for internal_FALSH run_from_flash.cmm *                               script for RAM: run_from_ram_vle.cmm * ********************************************************************************     BR, Petr

******************************************************************************** * Detailed Description: * This example shows how to use PIT module for triggering interrupts on its timeout. * * This example shows how to use PIT module for triggering interrupts on its timeout. * For closer details on how PIT works I suggest you to check reference manual as this is quite simple timer. * This example sets PIT timer0 channel0 for 5000000 cycles. * As soon as it exceeds the interrupt is triggered. * Pin state is toggling in ISR * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

This is simple example of the usage of Flash Array Integrity Check (FAIC) function that is available on all MPC56xx devices.   The FAIC reads data from selected and unlocked flash blocks and calculates the MISR signature. User can compare the MISR signature calculated by flash controller (in runtime) with MISR calculated by offline tool (this is done during development, not in runtime) from s-record file. If the MISR is identical, we know that the content of selected flash blocks corresponds to content in s-record file and that there are no ECC errors (single bit or double bit ECC errors).

******************************************************************************** * Detailed Description: * This example shows how to configure Wake up unit and CAN sampler. * Once the device is woken up from STOP mode by falling edge on CAN0RX pin, * the CAN sampler starts to sample this pin in given period. * FlexCAN module is not initialized and used in this example because the CAN * sampler is independent of FlexCAN. * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC560B 176LQFP, PPC5607B * Target :  internal_FLASH, RAM * Fsys:     64 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * * ------------------------------------------------------------------------------ * Test HW:  TRK-MPC5604P, SPC5604P * Maskset:  0M36W * Target :  RAM * Terminal: no * Fsys:     64 MHz PLL with 8 MHz crystal reference in RUN0. IRC in DRUN * * 1. you have to use an external power supply to the board (SBC power)   2. The SBC chip must be initialized (via SPI interface) to turn on the CAN transceiver.   3. For ease of use, install the VSUP shunt on (jumper J5). This it to put 9 V on the SBC's DBG pin - refer to the SBC Data Sheet for more details about the DBG pin of the SBC chip.   4. This code initializes the MCU, then sends commands to the SBC chip over the SPI bus to turn on the CAN transceiver, then the FlexCAN_0 module transmits a message out of the board.   I/O configuration for the TRK-MPC5604P CAN example:   MCU_PB0 -> SBC_TXD  (MPC5604P CAN0TX PCR[16] ALT1 function) MCU_PB1 <- SBC_RXD  (MPC5604P CAN0RX PCR[17] input function)   SPI bus between the MCU and SBC:   MCU_PC4 -> SBC_!CS    (MPC5604P DSPI_0 CS0  ALT1 function PCR[36]) MCU_PC5 -> SBC_CLK    (MPC5604P DSPI_0 SCK  ALT1 function PCR[37]) MCU_PC6 -> SBC_MOSI   (MPC5604P DSPI_0 SOUT ALT1 function PCR[38]) MCU_PC7 <- SBC_MISO   (MPC5604P DSPI_0 SIN  input function PCR[39])  * ********************************************************************************

This demo performs a communication on LIN bus between two MPC5604B EVBs.   LinFlex0 LIN Master ******************************************************************************** * Detailed Description: * - send header from a LIN Master * - either receive data from a LIN Slave or transmit a data * - no interrupt is used, just SW pooling * * ------------------------------------------------------------------------------ * Test HW:  XPC560B 144 LQFP MINIMODULE, XPC56XX EVB MOTHERBOARD, SPC5604B 2M27V * Target :  internal_RAM, Flash * LinFlex0: Lin Master, 19200 baudrate * Fsys:     64 MHz PLL with 8 MHz crystal reference * * ------------------------------------------------------------------------------ * EVB connections and jumper configuration * * XPC56XX EVB MOTHERBOARD * for LinFlex0 connection to the MC33661 LIN transceiver: * - RXDA_SEL (near SCI !!!!) jumper over pins 1-2 * - TXDA_SEL (near SCI) jumper over 1-2 * * for LIN Master functionality * - VSUP (J6) jumper fitted *   lin xceiver will get +12V from the EVB * - V_BUS (J14) jumper not fitted * - MASTER_EN jumper fitted * - LIN_EN jumper fitted * ********************************************************************************     LinFlex0 LIN Slave ******************************************************************************** * Detailed Description: * - receive header from a LIN Master * - either receive data from a LIN Master or transmit a data * - Filter can be enabled with the FILT_EN = 1 * - If filter is enabled TX interrupt is used to prepare data to send and *    RX interrupt to read received data * - If filter is disabled SW polling is used * * ------------------------------------------------------------------------------ * Test HW:  XPC560B 144 LQFP MINIMODULE, XPC56XX EVB MOTHERBOARD, SPC5604B 2M27V * Target :  internal_RAM * LinFlex0: Lin Slave, 19200 baudrate * Fsys:     64 MHz PLL with 8 MHz crystal reference * * ------------------------------------------------------------------------------ * EVB connections and jumper configuration * * XPC56XX EVB MOTHERBOARD * for LinFlex0 connection to the MC33661 LIN transceiver: * - RXDA_SEL (near SCI !!!!) jumper over pins 1-2 * - TXDA_SEL (near SCI) jumper over pins 1-2 * * for LIN Slave functionality * - VSUP (J6) jumper not fitted ...LIN transceiver will get +12V from the Master * - V_BUS jumper not fitted * - MASTER_EN jumper not fitted * - LIN_EN jumper fitted * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configures the FlexCAN to transmit and receive a CAN message. * ECC reporting in the FlexCAN module is enabled. * * In this config, CAN_A transmits a message. CAN_B receives the message. * CAN_A MB8 is configured to send data. CAN_A sends message each 1sec. * This interval is generated by PIT. * CAN_B MB9 is configured to receive a message, SW polling is used. * * Install jumpers J37 1-2 and J38 1-2 * * Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to use FCCU module for fake fault injection in order to test FCCU functionality. * * For closer details on how FCCU works I suggest you to check reference manual as this module is quite complex. * This example sets system clock for 200MHz running from PLL0 module. * The FCCU_Fake_fault_inject function is setting and injecting FCCU fault NCF[7] - STCU2 fault condition. * Short reset is triggered as soon as FCCU registers injected fault. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

External Bus Interface FAQs related to MPC55xx and MPC56xx MCUs Preliminary version

******************************************************************************** * Detailed Description: * This example content a driver for ADC module. * Basic ADC functionality is demonstrated via ADC_0 normal conversion for ADC_0 AN0 channel. * * For closer details on how ADC works I suggest you to check reference manual. * This example sets system clock for 200MHz running from PLL0 module. * Example contains basic ADC functionality demonstration. Software is starting normal ADC conversion * on ADC_0 channel AN0. * To demonstrate the measurement functionality on Freescale MPC57xx motherboard connect jumper to J53. * By doing this the potentiometer is connected to AN0 ADC input. For further details see MPC57xx EVB schematics. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to reprogram the shadow flash. * * It is highly recommended to read application note "Preventing Device Lockout * via Censorship on MPC55xx and MPC563x Families" * http://www.freescale.com/files/32bit/doc/app_note/AN3787.pdf * * This examples erases the shadow flash, then it restores censorship information * and then NVUSRO nonvolatile register is reprogrammed to disable the watchdog. * The watchdog is disabled by clearing of bit WATCHDOG_EN in NVUSRO. It ensures * that watchdog is disabled automatically during startup of MCU. * Watchdog can be also disabled by software (shown in the code). * * It is important to execute the code from RAM memory because Read-While-Write * is not supported here. * * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC560B 144LQFP, SPC5604B, silicon mask set 2M27V * Target :  internal_FLASH, RAM * ********************************************************************************

This simple example shows the ADC setting for the scan mode and usage of Trimmer on TRK-MPC5604P board. Use Trimmer to dim the LED1.   Regards, Petr     ******************************************************************************** * Detailed Description: * * ADC testing and usage of Trimmer on TRK board * * ------------------------------------------------------------------------------ * Test HW:  TRK-MPC5604P * Maskset:  0M36W * Target :  internal_RAM * Terminal: no * Fsys:     64 MHz with 8 MHz XOSC reference * EVB connection: * * Use Trimmer to dim the LED1 * * NOTE! Be sure the ADC is powered, J21 5V jumper ON * ********************************************************************************

******************************************************************************** * Detailed Description: * Example configure DRUN mode with PLL running at 160MHz. * It also contain basic PIT and INTC driver for interrupt demonstration. * On PIT timer timeout the PIT is triggering an interrupt which is served in PIT interrupt * service routine. * ------------------------------------------------------------------------------ * Test HW:     X - PC5748G - MB (rev C) * MCU:          PPC5748GMMN6A * Maskset:    1N81M * Fsys:          160 MHz * Debugger:    Lauterbach Trace32 *               * Target:         Internal_FLASH * ********************************************************************************

The purpose of the example is to present advantage of streaming mode feature.   Example initializes eQADC module, converts specified command queue and displays results into terminal window. Used analog inputs ANB_0 and ANB_1 requires external connection to converted voltage (potentiometer) to see some valid numbers. Following channels are being converted: CH0 = signal ANB_0 (connect pot USER_DEV_RV2(J4-7) --> ANB_0 (J19-3)) CH1= signal ANB_1 (connect pot USER_DEV_RV3(J4-8) --> ANB_1 (J19-4)) CH2 = may be left open (example configures the pin to be pulled-up) CH3 = may be left open (example configures the pin to be pulled-down) Result are being filled to 2 result queues to see loop switching in the terminal window when advance trigger occurs (results are displayed in two columns, 1st column is related to Rqueue0, 2nd to Rqueue1). Advance trigger occurs when EVB's USER switch 1 is being pressed (considering USER_DEV_1D(J4-2) --> TPU_A0 (J22-1)). Repeat trigger is initiated automatically by PIT3 timer in 1 sec intervals. eQADC command filled by eDMA, results drained by interrupt service routines.   For detailed description SEE ATTACHED document.

******************************************************************************** * Detailed Description: * ECSM Error Generation Register EEGR is used to generate a non-correctable ECC * error in RAM. The bad data is accessed then, so the IVOR1 exception is * generated and handled. * This file shows also ECSM_combined_isr and how to correct the wrong data. * Use macro Induce_ECC_error_by_DMA_read to select whether ECC error will be * injected by DMA read or CPU read. * At the end of main file you can select particular ME/EE setup by * comment/uncomment of particular function calls. * * ------------------------------------------------------------------------------ * Test HW:        XPC563MKIT * MCU:            PPC5633MMLQ80 * Fsys:           80/60/40/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************