******************************************************************************** * Detailed Description: * * The example shows how to initialize 3 submodules to generate 120° phase shift * between submodules. * CNTR register of each submodule is initialized with shifted value when PWM * generators are disabled using FORCE feature. * * ------------------------------------------------------------------------------ * Test HW:  MPC5744P (MPC5744P-257DS + MPC577xx motherboard) * Maskset:  1N15P * Target :  internal_FLASH, RAM * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * P8.13    - A[12] .. FlexPWM A[2] output * P8.14    - A[13] .. FlexPWM B[2] output * P10.8    - C[7] .. FlexPWM A[1] output * P10.7    - C[6] .. FlexPWM B[1] output * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows how to use SPI module in extended SPI mode * - DSPI3 is configured as a master * - SPI1 is configured as a slave * - Frame size is configured to 32bit * - Two writes are necessary to load one 32bit frame to TX FIFO * - For more details about the timing settings see application note AN4830 * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH ********************************************************************************

******************************************************************************** * Detailed Description: * Example shows MCU's temperature measurement using internal temperature sensor. * After basic initialization, the code initializes and calibrates eQADC, reads * test flash content and performs all necessary ADC measurement to calculate die * temperature. Results are then displayed in the terminal window. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            264/200/150/60 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * ADC end of conversion event is triggering DMA transfer which automatically * moves ADC measurement results of ADC_1 channel_0 into buffer ADC_reseult. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0     Mar-11-2015     b21190(Vlna Peter)  Initial Version 1.1    Feb-21-2017     b21190(Vlna Peter)  ADC triggering DMA *******************************************************************************/

This example contains On-line BIST configuration for MPC5746R in GreenHills compiler. For more details refer to application note AN5427 * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Oct-19-2015     b21190(Vlna Peter)  Initial Version 1.1    Nov-11-2015    b21190(Vlna Peter)  Added PPL0 200MHz as system clock 1.2    Dec-02-2015    b21190(Vlna Peter)  Added Flash controller init 1.3     May-24-2016    nxa13250(Vlna Peter)Added Online BIST *******************************************************************************/* ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Oct-19-2015     b21190(Vlna Peter)  Initial Version 1.1    Nov-11-2015    b21190(Vlna Peter)  Added PPL0 200MHz as system clock 1.2    Dec-02-2015    b21190(Vlna Peter)  Added Flash controller init 1.3     May-24-2016    nxa13250(Vlna Peter)Added Online BIST *******************************************************************************/

This example contain Lauterbach programming script for Off-line BIST configuration with 90% coverage. For more details refer to application note AN5427 - Using the Built-in Self-Test (BIST) on the MPC5746R

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq. * DSPI_A is configured as master, DSPI_B is configured as slave. * DSPI modules are connected together by wires on EVB. * Four DMA descriptors are initialized: * - master transmit * - master receive * - slave transmit * - slave receive * All transfers are done by DMA, master sends/receives 8 words and slave * receives/sends 8 words. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU:             PPC5676RDMVY1 3N23A * Fsys:            180MHz * Debugger:        Lauterbach Trace32 * Target:          RAM, internal_FLASH * EVB connection:  PCSA0 (J29-1) -> PCSB0 (J30-1) *                  SIN_A (J29-7) -> SOUT_B (J30-8) *                  SOUT_A (J29-8) -> SIN_B (J30-7) *                  SCK_A (J29-9) -> SCK_B (J30-9) * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates basic interrupt functionality. * ------------------------------------------------------------------------------ * Test HW:  MPC56xx Motherboard + XPC564xB/C 208LQFP * Maskset:  0N32E * Target :  internal_FLASH * Fsys:     16MHz IRC as system clock ******************************************************************************** Revision History: 1.0     Mar-13-2017     b21190(Vlna Peter)  Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * MPU is initialized to cover all resources (flash, RAM, peripheral bridges). * All masters are allowed to read-write-execute from all resources. * * Simple test case is used to check the behavior of MPU in case of access * violation: * - the MPU is reconfigured to disable write access to first 1KB or RAM memory *   (0x4000_0000 - 0x4000_03FF). * - if we write this RAM area, machine check exception is triggered * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Fsys:            264MHz * Debugger:        Lauterbach Trace32 * Target:          RAM, internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * Example dimmes LED1 according on board potentiometr. LED2 and LED3 demostrates * ADC watchdog functionality. LED2 is turned on when signal level is below LOW * threshold, LED3 is turned on when signal is above HIGH threshold. * Example also displays coverted results to the terminal window. * ------------------------------------------------------------------------------ * Test HW:         XPC560B 100LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             PPC5604BE MLL 1M27V * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys:            64/48 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  - initialize PB[8] as ANS0: connect potentiometer to PB[8]                      pin, remove J30 jumper and connect J30.2 with P2.9                    - header J8 (LED_EN) fully fitted ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates how to configure CGM )clock generation module) * and supply by clock all main peripherals. * Example demonstrate FCCU fake fault injection for fault 15. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx EVB + MPC5777M minimodule * Maskset:  0N50N * Target :  internal_FLASH * Fsys:     200 MHz PLL * ******************************************************************************** Revision History: 1.0     Nov-04-2014     b21190(Vlna Peter)  Initial Version 1.1     Feb-04-2016     b21190(Vlna Peter)  Fixed Clock configuration 1.2    Feb-06-2017    b21190(Vlna Peter)  FCCU fake fault injection *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * Initializes the MCU including the FlexCAN peripherals. * Configures the FlexCAN to transmit and receive a CAN message. * * Individual RX masking was added to the last version of this example. * Three messages with different ID's are sent via FlexCAN_0 MB0 MB1 and MB2. * These messages are received by FlexCAN_1 MB0, MB1 and MB2 according to masking * register settings. * * For MB0 data receive is used interrupt. * * * ------------------------------------------------------------------------------ * Test HW:         S32R274RRUEVB, MPC57xx Motherboard * MCU:             S32R274KAMMM 1N58R * Fsys:            PLL0 240MHz *                    Z4 Core 120MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, debug_ram and release mode) * EVB connection: * * It is necessary to remove both J35 jumpers. * * * Connect J35.2 to PA14 (CAN_1 TX) * Connect J35.4 to PA15 (CAN_1 RX) * * CAN0 is connected internally to J37 (this pin is placed on daughter card) * * Connect CAN P5.2 to J37.2 (CAN_1 and CAN_0 CANL) * Connect CAN P5.1 to J37.1 (CAN_1 and CAN_0 CANH) * * This connection has to be observed, otherwise correct communication between * CAN modules is not guaranteed. * * ********************************************************************************

******************************************************************************** * Detailed Description: * * Application initializes SPI0 module as a master and SPI2 module as a slave. * Data are sent from master to slave and from slave to master. Simple * polling method is used to determine, when data were sent/received. * Received data are saved to global variables. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777M-512DS, MPC57xx Motherboard * MCU:             PPC5777MQMVA8 0N78H * Fsys:            PLL0 300MHz *                    PLL1 300MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, debug_ram mode, release mode) * EVB connection:  P18.12 to P14.13 (CS_0) *                    P11.4 to P8.13 (SCK) *                    P11.1 to P11.5 (SOUT - SIN) *                    P11.8 to P12.9 (SIN - SOUT) * * ********************************************************************************

This document shows, how to use CodeWarrior 10.6 to program QSPI flash for Power Architecture microcontrollers.   1) Create new project for appropriate microcontroller. 2) Open Debug configuration and duplicate one of the target.   3) Rename duplicated target (optional) 4) Choose the duplicated (renamed) target and click Edit button in Target settings tab.   5) In new screen, click Advanced Programming Options.   6) Check Use Alternative Algorithm and choose the algorithm you want to use. Algorithms are place in CodeWarrior installation folder. Full path is CodeWarrior_installation_folder\MCU\bin\plugins\support\EPPC\gdi\P&E\   7) On the screen Debug configuration, choose the file you want to program to QSPI flash.   Click Apply and Debug.

******************************************************************************** * Detailed Description: * * Configures the FlexCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. * Baudrate during arbitration phase is set to 500kbps, during data phase 2Mpbs. * * In this config, CAN_0 transmits a message. CAN_1 receives the message. * * EVB connection: * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * NOTE! Termination resistor (120Ohm) have to be placed on transceivers output * * ------------------------------------------------------------------------------ * Test HW:  X-MPC574xG-324DS + X-MPC574XG-MB * Maskset:  1N81M * Target :  FLASH * Fsys:     160 MHz PLL * ********************************************************************************

In order to enable the RappID bootloader. It needs to program the C:\Freescale\RAppIDBL\RBF_Files\MPC5744P.rbf file into the MCU. User can use S32DS to program the rbf file to MCU. After that the Rappid bootloader PC utility can communicate with the MCU.

******************************************************************************** * Detailed Description: * Example of core watchdog implementation on Cobra 55. It executes on core 0 * All the functions are in the file "watchdog.c" *WatchDogCreate(delay, FirstTimeout, SecondTimeout) -> create/configure the wathdog timer *WatchDogStart() -> start the watchdog timer *WatchDogService() -> acknowledge the watchdog timer * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-416DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************

This document shows, how to use CRC gen utility in CodeWarrior for MCU IDE.   1) Create new project in CodeWarrior. 2) Create a file calc_crc.crc in the Project/Project_Settings/Linker_File directory. 3) Open project settings, choose C/C++ Build ->Settings and add the following command to Post-build steps: "${MCU_TOOLS_HOME}/bin/crcgen.exe" "${BuildLocation}/${BuildArtifactFileName}" -crc "${ProjDirPath}/Project_Settings/Linker_Files/calc_crc.crc" -srec "${BuildLocation}/${BuildArtifactFileName}.crc.mot" 26   4) Open calc_crc.crc and configure required parameters. Meaning of single lines is described in CodeWarrior reference manual called Targeting_Microcontrollers I used following code (it is only example)   5) Build your project. 6) File MPC5604B-CRCTest.elf.crc.mot was created   Now you have s-record, which contains CRC and which could be loaded to microcontroller.

******************************************************************************** * Detailed Description: * This SW provides the example of clearing of FCCU faults. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference + FCCU fault clearing example code. * ******************************************************************************** Revision History: 1.0     Jan-05-2016     nxa13250(Vlna Peter)  Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * 200 MHz PLL with 40 MHz crystal reference + FCCU fault clearing *           example code + FCCU ALARM state configuration * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************