******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminals ECHO. * * * Test HW:        X-MPC5744PE257DC, MPC57xx motherboard * MCU:              PPC5744PFMMM8 1N65H * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:             200 MHz * Debugger:      Lauterbach Trace32 *                       PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to A0 (P8.0), * ********************************************************************************

******************************************************************************** * Detailed Description: * This example content a driver for ADC module. * Basic ADC functionality is demonstrated via ADC_0 normal conversion for ADC_0 AN0 channel. * * For closer details on how ADC works I suggest you to check reference manual. * This example sets system clock for 200MHz running from PLL0 module. * Example contains basic ADC functionality demonstration. Software is starting normal ADC conversion * on ADC_0 channel AN0. * To demonstrate the measurement functionality on Freescale MPC57xx motherboard connect jumper to J53. * By doing this the potentiometer is connected to AN0 ADC input. For further details see MPC57xx EVB schematics. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to use PIT module for triggering interrupts on its timeout. * * This example shows how to use PIT module for triggering interrupts on its timeout. * For closer details on how PIT works I suggest you to check reference manual as this is quite simple timer. * This example sets PIT timer0 channel0 for 5000000 cycles. * As soon as it exceeds the interrupt is triggered. * Pin state is toggling in ISR * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * * LINFlexD_1 configured as Master *   - sends Header *   - either transmits a data to LIN Slave or receives data from a LIN Slave *   - no interrupt is used, just SW pooling * * LINFlexD_0 as Slave *   - receives header from a LIN Master *   - either receives data from a LIN Master or transmits a data to Master *   - filter is enabled *   - TX interrupt is used to prepare data to send and *   - RX interrupt to read received data * * EVB connection: * *   Switches on Motherboard: *   P6.1 to P8.1  ... SW1 to PA0 *   P6.2 to P8.2  ... SW2 to PA1 *   P6.3 to P8.3  ... SW3 to PA2 *   P6.4 to P8.4  ... SW4 to PA3 * *   Unconnect LINFlexD_0 from UART transceiver *   J14 SCI_RX open *   J13 SCI_TX open * *   As only single LIN transceiver is available LINFlex modules are connected *   together before this transceiver in the way TX pins together and RX pins together. *   TX pins must be configured as open drain and use a pullup resistor. * *   P11.15 to P12.8    TX pins *   P11.16 to P12.7    RX pins * *   Connect LINFlexD_1 to LIN transceiver on Motherboard *   J17 - LIN_TX ON *   J16 - LIN_RX ON *   J15 - LIN_EN ON *   P3 1-2 ON ... VSUP to 12V ** *   See LIN signal on P3.3 or J4.4. * * ------------------------------------------------------------------------------ * Test HW:  MPC5744P * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: None ******************************************************************************** Revision History: 1.0     Feb-22-2016     PetrS          Initial Version of LIN example *******************************************************************************/ Original Attachment has been moved to: Example-MPC5744P-LINFlex-LIN-Master-Slave-test-v1_0-GHS614.zip

******************************************************************************** * Detailed Description: * * Example shows MCU's temperature measurement with the help of TSENS. * Calibartion constants for TSENS0 and TSENS1 are read from Test Flash and * ADC0/ADC1 is set to measure Vbg and TSENS outputs. * Calculated internal temperature can be desplayed on the Terminal. * * EVB connection: * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * See results on PC terminal (19200, 8N1, None). You should get following text * (with different values for sure) * * TSENS0/TSENS1 temperature measurement * press any key to continue... * * Calibration constants read from Test Flash * * TSENS0                           TSENS1 * * K1 = 429                         K1 = -220 * K2 = -5785                       K2 = -5767 * K3 = -12800                      K3 = -12736 * K4 = 45                          K4 = 45 * *      K1 * Vbg_code * 2^-1 + K2 * TSENS_code * 2^3 * T = ------------------------------------------------------------------------- / 4 - 273.15 [degC] *     [K3 * Vbg_code * 2^2 + K4 * TSENS_code] * 2^-10 * * Vbg0_code      = 1502               Vbg1_code      = 1502 * TSENS0_code = 2002               TSENS1_code = 1988 * * TSENS0 temp = 34.57 degC         TSENS1 temp = 36.78 degC * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

******************************************************************************** * Detailed Description: * * ------------------------------------------------------------------------------ * Test HW:  TRK-MPC5604P, SPC5604P * Maskset:  0M36W * Target :  RAM * Terminal: no * Fsys:     64 MHz PLL with 8 MHz crystal reference in RUN0. IRC in DRUN * * 1. you have to use an external power supply to the board (SBC power)   2. The SBC chip must be initialized (via SPI interface) to turn on the CAN transceiver.   3. For ease of use, install the VSUP shunt on (jumper J5). This it to put 9 V on the SBC's DBG pin - refer to the SBC Data Sheet for more details about the DBG pin of the SBC chip.   4. This code initializes the MCU, then sends commands to the SBC chip over the SPI bus to turn on the CAN transceiver, then the FlexCAN_0 module transmits a message out of the board.   I/O configuration for the TRK-MPC5604P CAN example:   MCU_PB0 -> SBC_TXD  (MPC5604P CAN0TX PCR[16] ALT1 function) MCU_PB1 <- SBC_RXD  (MPC5604P CAN0RX PCR[17] input function)   SPI bus between the MCU and SBC:   MCU_PC4 -> SBC_!CS    (MPC5604P DSPI_0 CS0  ALT1 function PCR[36]) MCU_PC5 -> SBC_CLK    (MPC5604P DSPI_0 SCK  ALT1 function PCR[37]) MCU_PC6 -> SBC_MOSI   (MPC5604P DSPI_0 SOUT ALT1 function PCR[38]) MCU_PC7 <- SBC_MISO   (MPC5604P DSPI_0 SIN  input function PCR[39])  * ********************************************************************************

******************************************************************************** * Detailed Description: * * CAN0 module is configured to transmit one message with ID 0x555 to CAN1 * module. CAN1 module is configured to use DMA to receive the message. * Once the DMA module reads the received frame, interrupt is triggered. * Follow application note AN4830 regarding the CAN settings. * http://www.freescale.com/files/microcontrollers/doc/app_note/AN4830.pdf * http://www.freescale.com/files/microcontrollers/doc/app_note/AN4830SW.zip * The example from AN4830 is modified to use DMA and RXFIFO on CAN1 module. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * Example show simple flash programming routine. During runtime it changes * content of field of constants 'test' (thus located in internal flash). * Also it shows how to relocate code into RAM a data into FLASH (used linker * command file is MPC5643L_my_sections.lcf and MPC5643L_DEBUG_my_sections.lcf). * * Note: For complex tasks use SSD driver (Freescale site for particular device, * Software&Tools/Run-Time Software/Middleware-Device Drivers * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH, RAM * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON) * by initialization of instruction/data cache and enabling of branch prediction. * Example suppose MCU is configured for LSM (Lock-step mode). * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:        MPC5675KEVB * MCU:            PPC5675KFMMSJ in Lock-Step mode * Fsys:           180/150 MHz CORE_CLK * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

The example does exactly the same operation like this example: https://community.freescale.com/docs/DOC-105380 ...but SSD flash driver is used now.   ******************************************************************************** * Detailed Description: * * Unlock, erase and program of flash mid block 0x00FB_8000 - 0x00FB_FFFF. * Used SSD flash drivers: * http://www.freescale.com/files/product/software/C55_JDP_SSD.exe * Version of the driver is v1.0.0 * ------------------------------------------------------------------------------ * Test HW:    X - PC5748G - MB (rev C) * MCU:        PPC5748GMMN6A * Maskset:    1N81M * Fsys:       160 MHz * Debugger:   Lauterbach Trace32 *              * Target:     Internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to reprogram the shadow flash. * * It is highly recommended to read application note "Preventing Device Lockout * via Censorship on MPC55xx and MPC563x Families" * http://www.freescale.com/files/32bit/doc/app_note/AN3787.pdf * * This examples erases the shadow flash, then it restores censorship information * and then NVUSRO nonvolatile register is reprogrammed to disable the watchdog. * The watchdog is disabled by clearing of bit WATCHDOG_EN in NVUSRO. It ensures * that watchdog is disabled automatically during startup of MCU. * Watchdog can be also disabled by software (shown in the code). * * It is important to execute the code from RAM memory because Read-While-Write * is not supported here. * * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC560B 144LQFP, SPC5604B, silicon mask set 2M27V * Target :  internal_FLASH, RAM * ********************************************************************************

******************************************************************************** * Detailed Description: * This example initializes SMPU_0 and SMPU_1 to cover all memory resources for * all masters. * Simple test is performed in this example: after initialization, SMPU_1 * configuration is changed to disable write access to last 4kB of RAM for * Process ID 1. Write acess is allowed for Process ID 0. * If this area is written by CPU while the Process ID is 1, exception will * occur due to access violation. * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * Enable external interrupt on pin PA[3]. * If falling edge is detected, interrupt is triggered and LED1 on PE[4] is * toggled. * * Connect external signal to PA[3] or connect push button by wire. * * ------------------------------------------------------------------------------ * Test HW:  TRK-MPC5606B, SPC5606B 0N32E * Target :  internal_FLASH, RAM * Fsys:     64 MHz PLL with 8 MHz crystal reference * ********************************************************************************

******************************************************************************** * Detailed Description: * * Simple LINFlex UART mode transmit and receive without interrupts (polled UART) * TXFIFO and RXFIFO macro is used to select between buffer and FIFO mode * * EVB connection: * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * See results on PC terminal (19200, 8N1, None). * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

This config tool simplifies PLL setting calculation and clock configuration for MPC5744P device.                  Follow these steps                  Note: Macros have to be enabled!                  1. Enter frequency of used XOSC and desired PLL0 and PLL1 output.                 - put values into cells B11, Q10 and Q17 of the "Clocks" sheet                 - check if it is Valid or Invalid                 - "PLLconfig" sheet shows possible PLLs configurations                  2. Configure System and AUX clock selectors and its Dividers                 - check calculated frequency of System/Peripheral clocks                 - if Invalid change source clock and Divider value to keep Max freq                    3. Copy generated code by pressing "Copy Code" button

External Bus Interface FAQs related to MPC55xx and MPC56xx MCUs Preliminary version

******************************************************************************** * Detailed Description: * Used flash driver:  MPC5700 C55FG Flash Standard Software Driver (REV 1.1.0) * http://www.nxp.com/files/product/software/C55_JDP_SSD.exe * * This example checks four large 256KB flash blocks at address 0x0100_0000 - * 0x010F_FFFF. * Some random data are placed to this section (constant "flash_data[]"), so the * s-record is not empty. * It is necessary to use off-line MISR_C55.exe tool which calculates MISR * values for selected flash blocks. See the "MISR gen" folder included in this * project. File "core0.run" is s-record file which is used for calculation. It * contains the data (constant "flash_data[]") placed to the selected blocks. * "misr.bat" file shows how to call the calculator. * "output.txt" contains the result of this operation - the MISR values. * Once this is done, initialize the SSD drivers, unlock blocks which are going * to be checked and run the FlashArrayIntegrityCheck function. * Notice that the code must be executed from RAM. We cannot access the flash * during this operation. If the operation is successful, FlashCheckStatus will * return opResult C55_OK if the MISR values are equal. It will return * C55_ERROR_MISMATCH if the MISR values are not equal, i.e. the flash is * corrupted and the content does not correspond to s-record file. * ------------------------------------------------------------------------------ * Test HW:         X-MPC5744PE257DC, MPC57xx motherboard * MCU:             PPC5744PFMMM8 1N65H * Fsys:            200 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * Initializes the MCU including the FlexCAN peripherals. * Configures the FlexCAN to transmit and receive a CAN message. * * Individual RX masking was added to the last version of this example. * Three messages with different ID's are sent via FlexCAN_0 MB0 MB1 and MB2. * These messages are received by FlexCAN_1 MB0, MB1 and MB2 according to masking * register settings. * * For MB0 data receive is used interrupt. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection: * * It is necessary to remove both J32 jumpers and also both J35 jumpers. * * Connect J32.2 to PC9 (CAN_0 TX) * Connect J32.4 to PC8 (CAN_0 RX) * * Connect J35.2 to PE5 (CAN_1 TX) * Connect J35.4 to PG14 (CAN_1 RX) * * Connect CAN P5.2 to CAN2 P4.2 (CAN_0 and CAN_1 CANL) * Connect CAN P5.1 to CAN2 P4.1 (CAN_0 and CAN_1 CANH) * * This connection has to be observed, otherwise correct communication between * CAN modules is not guaranteed. * * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows possible implementation of frequency and duty cycle * measurement with the help of eMIOS module. * Two eMIOS channels are used and set to IPWM and IPM modes. The first channel * measures the positive pulse width and the second channel measures the period. * * EVB connection: * PJ7.5 to PJ7.6 ... connect external pulse signal to this * * See result on PC terminal (9600, 8N1) * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC564xB/C, SPC5646C 0N32E silicon * Target :  internal_FLASH, RAM * Fsys:     120 MHz PLL0 * Debugger: Lauterbach Trace32. script for internal_FALSH run_from_flash.cmm *                               script for RAM: run_from_ram_vle.cmm * ********************************************************************************     BR, Petr

******************************************************************************** * Detailed Description: * Example configure DRUN mode with PLL running at 160MHz. * It also contain basic PIT and INTC driver for interrupt demonstration. * On PIT timer timeout the PIT is triggering an interrupt which is served in PIT interrupt * service routine. * ------------------------------------------------------------------------------ * Test HW:     X - PC5748G - MB (rev C) * MCU:          PPC5748GMMN6A * Maskset:    1N81M * Fsys:          160 MHz * Debugger:    Lauterbach Trace32 *               * Target:         Internal_FLASH * ********************************************************************************