Error Correcting Codes Implemented on MPC5744P Please be aware this is PRELIMINARY document and may be changed without notice.   Related code examples can be found here: Example 1 - MPC5744P 1b+2b_RAM_ECC_error_injection GHS714  Example 2 - MPC5744P 1b+2b_PERRAM_ECC_error_injection GHS614  Example 3 - MPC5744P 1b+2b_FLASH_ECC_error_by_UTEST_area_read GHS614  Example 4 - MPC5744P EDC_after_ECC_error_by_UTEST_area_read GHS714 

This is simple example of the usage of Flash Array Integrity Check (FAIC) function that is available on all MPC56xx devices.   The FAIC reads data from selected and unlocked flash blocks and calculates the MISR signature. User can compare the MISR signature calculated by flash controller (in runtime) with MISR calculated by offline tool (this is done during development, not in runtime) from s-record file. If the MISR is identical, we know that the content of selected flash blocks corresponds to content in s-record file and that there are no ECC errors (single bit or double bit ECC errors).

This demo performs a communication on LIN bus between two MPC5604B EVBs.   LinFlex0 LIN Master ******************************************************************************** * Detailed Description: * - send header from a LIN Master * - either receive data from a LIN Slave or transmit a data * - no interrupt is used, just SW pooling * * ------------------------------------------------------------------------------ * Test HW:  XPC560B 144 LQFP MINIMODULE, XPC56XX EVB MOTHERBOARD, SPC5604B 2M27V * Target :  internal_RAM, Flash * LinFlex0: Lin Master, 19200 baudrate * Fsys:     64 MHz PLL with 8 MHz crystal reference * * ------------------------------------------------------------------------------ * EVB connections and jumper configuration * * XPC56XX EVB MOTHERBOARD * for LinFlex0 connection to the MC33661 LIN transceiver: * - RXDA_SEL (near SCI !!!!) jumper over pins 1-2 * - TXDA_SEL (near SCI) jumper over 1-2 * * for LIN Master functionality * - VSUP (J6) jumper fitted *   lin xceiver will get +12V from the EVB * - V_BUS (J14) jumper not fitted * - MASTER_EN jumper fitted * - LIN_EN jumper fitted * ********************************************************************************     LinFlex0 LIN Slave ******************************************************************************** * Detailed Description: * - receive header from a LIN Master * - either receive data from a LIN Master or transmit a data * - Filter can be enabled with the FILT_EN = 1 * - If filter is enabled TX interrupt is used to prepare data to send and *    RX interrupt to read received data * - If filter is disabled SW polling is used * * ------------------------------------------------------------------------------ * Test HW:  XPC560B 144 LQFP MINIMODULE, XPC56XX EVB MOTHERBOARD, SPC5604B 2M27V * Target :  internal_RAM * LinFlex0: Lin Slave, 19200 baudrate * Fsys:     64 MHz PLL with 8 MHz crystal reference * * ------------------------------------------------------------------------------ * EVB connections and jumper configuration * * XPC56XX EVB MOTHERBOARD * for LinFlex0 connection to the MC33661 LIN transceiver: * - RXDA_SEL (near SCI !!!!) jumper over pins 1-2 * - TXDA_SEL (near SCI) jumper over pins 1-2 * * for LIN Slave functionality * - VSUP (J6) jumper not fitted ...LIN transceiver will get +12V from the Master * - V_BUS jumper not fitted * - MASTER_EN jumper not fitted * - LIN_EN jumper fitted * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start one Z7 core, interrupts initialization, ICache and DCache are disabled * on both cores because of shared memory, which must not be cached. * * There is 4K shared memory defined in the linker file. This memory is used by * both cores. Both cores access into the structure, which is placed in the shared * memory. This access is marked as a critical section. Only one core can write * to the structure at the same time. To ensure this, there are Gates, which * guarantee data coherence during the access. Only one core can be in critical * section. Second core has to wait, until first core leaves the critical section * * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3B 0N76P * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz *                    Z7 Core 266MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  default connection * ********************************************************************************

The aim of the MPC5643L PWM triggered measurement concept is to introduce hardware  subsystem concept of autonomous triggering of ADC measurement by PWM module in desired time intervals and automatic storing of measured data into buffer located in SRAM. This autonomous measurement concept will offload the microprocessor’s core and presents the very precise way how to achieve the ADC time critical measurement synchronized with PWM signal generated by FlexPWM module.

This document summarizes simple I2C driver implementation for MPC5xxx devices. The code follows Reference Manual's Flow-Chart of Typical I2C Interrupt Routine.

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminals ECHO. * * * Test HW:        X-MPC5744PE257DC, MPC57xx motherboard * MCU:              PPC5744PFMMM8 1N65H * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:             200 MHz * Debugger:      Lauterbach Trace32 *                       PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to A0 (P8.0), * ********************************************************************************

******************************************************************************** * Detailed Description: * This example content a driver for ADC module. * Basic ADC functionality is demonstrated via ADC_0 normal conversion for ADC_0 AN0 channel. * * For closer details on how ADC works I suggest you to check reference manual. * This example sets system clock for 200MHz running from PLL0 module. * Example contains basic ADC functionality demonstration. Software is starting normal ADC conversion * on ADC_0 channel AN0. * To demonstrate the measurement functionality on Freescale MPC57xx motherboard connect jumper to J53. * By doing this the potentiometer is connected to AN0 ADC input. For further details see MPC57xx EVB schematics. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * * Example shows MCU's temperature measurement with the help of TSENS. * Calibartion constants for TSENS0 and TSENS1 are read from Test Flash and * ADC0/ADC1 is set to measure Vbg and TSENS outputs. * Calculated internal temperature can be desplayed on the Terminal. * * EVB connection: * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * See results on PC terminal (19200, 8N1, None). You should get following text * (with different values for sure) * * TSENS0/TSENS1 temperature measurement * press any key to continue... * * Calibration constants read from Test Flash * * TSENS0                           TSENS1 * * K1 = 429                         K1 = -220 * K2 = -5785                       K2 = -5767 * K3 = -12800                      K3 = -12736 * K4 = 45                          K4 = 45 * *      K1 * Vbg_code * 2^-1 + K2 * TSENS_code * 2^3 * T = ------------------------------------------------------------------------- / 4 - 273.15 [degC] *     [K3 * Vbg_code * 2^2 + K4 * TSENS_code] * 2^-10 * * Vbg0_code      = 1502               Vbg1_code      = 1502 * TSENS0_code = 2002               TSENS1_code = 1988 * * TSENS0 temp = 34.57 degC         TSENS1 temp = 36.78 degC * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to use PIT module for triggering interrupts on its timeout. * * This example shows how to use PIT module for triggering interrupts on its timeout. * For closer details on how PIT works I suggest you to check reference manual as this is quite simple timer. * This example sets PIT timer0 channel0 for 5000000 cycles. * As soon as it exceeds the interrupt is triggered. * Pin state is toggling in ISR * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * * ------------------------------------------------------------------------------ * Test HW:  TRK-MPC5604P, SPC5604P * Maskset:  0M36W * Target :  RAM * Terminal: no * Fsys:     64 MHz PLL with 8 MHz crystal reference in RUN0. IRC in DRUN * * 1. you have to use an external power supply to the board (SBC power)   2. The SBC chip must be initialized (via SPI interface) to turn on the CAN transceiver.   3. For ease of use, install the VSUP shunt on (jumper J5). This it to put 9 V on the SBC's DBG pin - refer to the SBC Data Sheet for more details about the DBG pin of the SBC chip.   4. This code initializes the MCU, then sends commands to the SBC chip over the SPI bus to turn on the CAN transceiver, then the FlexCAN_0 module transmits a message out of the board.   I/O configuration for the TRK-MPC5604P CAN example:   MCU_PB0 -> SBC_TXD  (MPC5604P CAN0TX PCR[16] ALT1 function) MCU_PB1 <- SBC_RXD  (MPC5604P CAN0RX PCR[17] input function)   SPI bus between the MCU and SBC:   MCU_PC4 -> SBC_!CS    (MPC5604P DSPI_0 CS0  ALT1 function PCR[36]) MCU_PC5 -> SBC_CLK    (MPC5604P DSPI_0 SCK  ALT1 function PCR[37]) MCU_PC6 -> SBC_MOSI   (MPC5604P DSPI_0 SOUT ALT1 function PCR[38]) MCU_PC7 <- SBC_MISO   (MPC5604P DSPI_0 SIN  input function PCR[39])  * ********************************************************************************

******************************************************************************** * Detailed Description: * * LINFlexD_1 configured as Master *   - sends Header *   - either transmits a data to LIN Slave or receives data from a LIN Slave *   - no interrupt is used, just SW pooling * * LINFlexD_0 as Slave *   - receives header from a LIN Master *   - either receives data from a LIN Master or transmits a data to Master *   - filter is enabled *   - TX interrupt is used to prepare data to send and *   - RX interrupt to read received data * * EVB connection: * *   Switches on Motherboard: *   P6.1 to P8.1  ... SW1 to PA0 *   P6.2 to P8.2  ... SW2 to PA1 *   P6.3 to P8.3  ... SW3 to PA2 *   P6.4 to P8.4  ... SW4 to PA3 * *   Unconnect LINFlexD_0 from UART transceiver *   J14 SCI_RX open *   J13 SCI_TX open * *   As only single LIN transceiver is available LINFlex modules are connected *   together before this transceiver in the way TX pins together and RX pins together. *   TX pins must be configured as open drain and use a pullup resistor. * *   P11.15 to P12.8    TX pins *   P11.16 to P12.7    RX pins * *   Connect LINFlexD_1 to LIN transceiver on Motherboard *   J17 - LIN_TX ON *   J16 - LIN_RX ON *   J15 - LIN_EN ON *   P3 1-2 ON ... VSUP to 12V ** *   See LIN signal on P3.3 or J4.4. * * ------------------------------------------------------------------------------ * Test HW:  MPC5744P * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: None ******************************************************************************** Revision History: 1.0     Feb-22-2016     PetrS          Initial Version of LIN example *******************************************************************************/ Original Attachment has been moved to: Example-MPC5744P-LINFlex-LIN-Master-Slave-test-v1_0-GHS614.zip

******************************************************************************** * Detailed Description: * * CAN0 module is configured to transmit one message with ID 0x555 to CAN1 * module. CAN1 module is configured to use DMA to receive the message. * Once the DMA module reads the received frame, interrupt is triggered. * Follow application note AN4830 regarding the CAN settings. * http://www.freescale.com/files/microcontrollers/doc/app_note/AN4830.pdf * http://www.freescale.com/files/microcontrollers/doc/app_note/AN4830SW.zip * The example from AN4830 is modified to use DMA and RXFIFO on CAN1 module. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit ECC * error in internal FLASH (user must choose it in the option at the end of main * function). * ECC error is injected by reading of pre-defined patterns in UTEST area at * addresses 0x00400040 and 0x00400060. * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

******************************************************************************** * Detailed Description: * Example show simple flash programming routine. During runtime it changes * content of field of constants 'test' (thus located in internal flash). * Also it shows how to relocate code into RAM a data into FLASH (used linker * command file is MPC5643L_my_sections.lcf and MPC5643L_DEBUG_my_sections.lcf). * * Note: For complex tasks use SSD driver (Freescale site for particular device, * Software&Tools/Run-Time Software/Middleware-Device Drivers * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH, RAM * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON) * by initialization of instruction/data cache and enabling of branch prediction. * Example suppose MCU is configured for LSM (Lock-step mode). * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:        MPC5675KEVB * MCU:            PPC5675KFMMSJ in Lock-Step mode * Fsys:           180/150 MHz CORE_CLK * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

The example does exactly the same operation like this example: https://community.freescale.com/docs/DOC-105380 ...but SSD flash driver is used now.   ******************************************************************************** * Detailed Description: * * Unlock, erase and program of flash mid block 0x00FB_8000 - 0x00FB_FFFF. * Used SSD flash drivers: * http://www.freescale.com/files/product/software/C55_JDP_SSD.exe * Version of the driver is v1.0.0 * ------------------------------------------------------------------------------ * Test HW:    X - PC5748G - MB (rev C) * MCU:        PPC5748GMMN6A * Maskset:    1N81M * Fsys:       160 MHz * Debugger:   Lauterbach Trace32 *              * Target:     Internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * A simple example configures eTPU engine B channels 0/1 for GPO/GPI. It is * needed to connect these pins by wire. Output wave is generated by eTPU GPIO * output function and inputs are read by fs_etpu_gpio_input_immed function * latching just current pin state. Pin history is displayed in ISR. * * Note: It is needed to configure IGF module, otherwise inputs does not pass * to eTPU module. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUB0 (PortR P25-1) --> ETPUB1 (PortR P25-0) by wire * ********************************************************************************

Detailed Description:                      This config tool simplifies DCF records calculation for MPC5777C device.                 Look at HowToUse sheet for simple guideline, then work with DCF sheet                 Notes: - Macros have to be enabled!       - Programming more than 104 DCF records on Cut1.0b will result in incorrect device operation (FCCU faults, SSCM[CER] bit set, etc)       BR, Petr

******************************************************************************** * Detailed Description: * This example initializes SMPU_0 and SMPU_1 to cover all memory resources for * all masters. * Simple test is performed in this example: after initialization, SMPU_1 * configuration is changed to disable write access to last 4kB of RAM for * Process ID 1. Write acess is allowed for Process ID 0. * If this area is written by CPU while the Process ID is 1, exception will * occur due to access violation. * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************