Detailed Description:  Initializes the MCU including the FlexCAN peripherals.  Configures the FlexCAN to transmit and receive a CAN message.  In this config, CAN_0 transmits a message. CAN_1 receives the message.  CAN_0 MB8 is configured to send data each 1sec.This interval is generated by PIT.  CAN_1 RXFIFO is configured to receive a message and interrupt for MB5 is enabled.  To connect FlexCAN0 module (MCU's PB0/PB1 pins) to the motherboard's transceiver  with J5 CAN DB9 connector you have to:  - connect J17 2-6 on daughter board  - connect J17 5-3 on daughter board  This should be done as default    To connect FlexCAN1 module (MCU's PA14/PA15 pins) to the motherboard's transceiver  with J6 CAN DB9 connector you have to:  - connect J37 2-3 on motherboard  - connect J38 2-3 on motherboard  Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1  Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2  Terminate the CAN bus by connecting a 60 ohm resistor between CANH and CANL  To see LED toggling connect P8.1 to USER LED (P7.x)  ------------------------------------------------------------------------------  Test HW:  MPC5744P EVB  Maskset:  1N65H  Target :  RAM, internal_FLASH  Fsys:     200 MHz PLL with 40 MHz crystal reference

A requirement of the standard is to detect the accumulation of latent defects. To meet this requirement the MPC5744P has the ability to execute Built-In Self-Test (BIST) procedures.

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start one Z7 core, interrupts initialization, ICache and DCache are disabled * on both cores because of shared memory, which must not be cached. * * There is 4K shared memory defined in the linker file. This memory is used by * both cores. Both cores access into the structure, which is placed in the shared * memory. This access is marked as a critical section. Only one core can write * to the structure at the same time. To ensure this, there are Gates, which * guarantee data coherence during the access. Only one core can be in critical * section. Second core has to wait, until first core leaves the critical section * * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3B 0N76P * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz *                    Z7 Core 266MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  default connection * ********************************************************************************

******************************************************************************** * Detailed Description: * * * This example shows synchronization between FlexPWM, CTU and ADC modules. * The FlexPWM Submodule 0 is initialized to generate PWM signal, and rising edge * of PWM B0 signal is used to generate trigger signal for CTU module. The CTU module * sends two commands to ADCs. Single conversion mode is used, so ADC0 ch0 and ch1 * are sampled. The conversion result is used to modify PWM B0 rising egde position * and change delay between external trigger and ADC sequence triggering. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P8.1  - A[0]  .. GPIO output, used to see CTU-ADC ISR period * P9.1     - B[7]  .. ADC0 AN[0] input * P9.2     - B[8]  .. ADC0 AN[1] input * P16.4 - I[3] .. CTU0 EXT TRG output   * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * * connect Trimmer J53.1 to P9.1 to change position of PWM B0 rising edge * connect Trimmer J53.1 to P9.2 to change CTU trigger delay from PWM B0 rising edge * * see CTU0 EXT TRG output signal (toggle on each trigger) on P16.4 with respect of PWM signals * ********************************************************************************

******************************************************************************** * Detailed Description: * * Example gives possible implementation of input signal period/freq measurement. * eTimer channel capture 1 and 2 features are used. CAPT1/CAPT2 capture counter * value on rising/falling edge of input signal. The FIFO is set to 2 entries * and ICF2 is monitored. Free-running mode is used here. * * eTimer channel 0-1 are cascaded to achieve 1sec/1Hz measuring with 32bit counter.   * EVB connection: *   P8.2  - A[1]  .. eTimer0 channel1 input signal *   P8.1  - A[0]  .. GPIO output, used to show measurement period * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * connect pulse signal to the P8.2. * See results on PC terminal (19200, 8N1, None). * Change freq/duty of input signal. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

This is simple example of the usage of Flash Array Integrity Check (FAIC) function that is available on all MPC56xx devices.   The FAIC reads data from selected and unlocked flash blocks and calculates the MISR signature. User can compare the MISR signature calculated by flash controller (in runtime) with MISR calculated by offline tool (this is done during development, not in runtime) from s-record file. If the MISR is identical, we know that the content of selected flash blocks corresponds to content in s-record file and that there are no ECC errors (single bit or double bit ECC errors).

Error Correcting Codes Implemented on MPC5744P Please be aware this is PRELIMINARY document and may be changed without notice.   Related code examples can be found here: Example 1 - MPC5744P 1b+2b_RAM_ECC_error_injection GHS714  Example 2 - MPC5744P 1b+2b_PERRAM_ECC_error_injection GHS614  Example 3 - MPC5744P 1b+2b_FLASH_ECC_error_by_UTEST_area_read GHS614  Example 4 - MPC5744P EDC_after_ECC_error_by_UTEST_area_read GHS714 

******************************************************************************** * Detailed Description: * A simple example configures eTPU engine B channels 0/1 for GPO/GPI. It is * needed to connect these pins by wire. Output wave is generated by eTPU GPIO * output function and inputs are read by fs_etpu_gpio_input_immed function * latching just current pin state. Pin history is displayed in ISR. * * Note: It is needed to configure IGF module, otherwise inputs does not pass * to eTPU module. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUB0 (PortR P25-1) --> ETPUB1 (PortR P25-0) by wire * ********************************************************************************

Hello    If you want to do nothing on MCU, no-operation is used generally.     Additional mnemonics are provided for the preferred forms of no-op, like nop, e_nop, se_nop. (Where the semantics are similar but the binary encoding differ, the standard mnemonic is typically preceded with an e_ to denote a VLE instruction. To distinguish between similar instructions available in both 16- and 32-bit forms under VLE and standard instructions, VLE instructions encoded with 16 bits have an se_ prefix.)    When you compile these code within IDE, you can get the results as below. The code could run correctly except __asm__ ("nop").  Some MPC5xxx will stop at __asm__ ("nop").    "nop"         gives Book E NOP instruction which isn't valid on VLE only cores. "e_nop"     gives 32bit VLE instruction. "se_nop"   gives 16bit VLE instruction. Based on the summary within AN4802 (thanks for Randy Dee's working), Qorivva MPC57xx e200zx Core Differences, Book E is not supported by MPC57xx. VLE instruction set is supported only.   This is the reason that user should use "e_nop" or "se_nop" except "nop" on MPC57xx or S32R2xx. Cheers! Oliver

The aim of the MPC5643L PWM triggered measurement concept is to introduce hardware  subsystem concept of autonomous triggering of ADC measurement by PWM module in desired time intervals and automatic storing of measured data into buffer located in SRAM. This autonomous measurement concept will offload the microprocessor’s core and presents the very precise way how to achieve the ADC time critical measurement synchronized with PWM signal generated by FlexPWM module.

This demo performs a communication on LIN bus between two MPC5604B EVBs.   LinFlex0 LIN Master ******************************************************************************** * Detailed Description: * - send header from a LIN Master * - either receive data from a LIN Slave or transmit a data * - no interrupt is used, just SW pooling * * ------------------------------------------------------------------------------ * Test HW:  XPC560B 144 LQFP MINIMODULE, XPC56XX EVB MOTHERBOARD, SPC5604B 2M27V * Target :  internal_RAM, Flash * LinFlex0: Lin Master, 19200 baudrate * Fsys:     64 MHz PLL with 8 MHz crystal reference * * ------------------------------------------------------------------------------ * EVB connections and jumper configuration * * XPC56XX EVB MOTHERBOARD * for LinFlex0 connection to the MC33661 LIN transceiver: * - RXDA_SEL (near SCI !!!!) jumper over pins 1-2 * - TXDA_SEL (near SCI) jumper over 1-2 * * for LIN Master functionality * - VSUP (J6) jumper fitted *   lin xceiver will get +12V from the EVB * - V_BUS (J14) jumper not fitted * - MASTER_EN jumper fitted * - LIN_EN jumper fitted * ********************************************************************************     LinFlex0 LIN Slave ******************************************************************************** * Detailed Description: * - receive header from a LIN Master * - either receive data from a LIN Master or transmit a data * - Filter can be enabled with the FILT_EN = 1 * - If filter is enabled TX interrupt is used to prepare data to send and *    RX interrupt to read received data * - If filter is disabled SW polling is used * * ------------------------------------------------------------------------------ * Test HW:  XPC560B 144 LQFP MINIMODULE, XPC56XX EVB MOTHERBOARD, SPC5604B 2M27V * Target :  internal_RAM * LinFlex0: Lin Slave, 19200 baudrate * Fsys:     64 MHz PLL with 8 MHz crystal reference * * ------------------------------------------------------------------------------ * EVB connections and jumper configuration * * XPC56XX EVB MOTHERBOARD * for LinFlex0 connection to the MC33661 LIN transceiver: * - RXDA_SEL (near SCI !!!!) jumper over pins 1-2 * - TXDA_SEL (near SCI) jumper over pins 1-2 * * for LIN Slave functionality * - VSUP (J6) jumper not fitted ...LIN transceiver will get +12V from the Master * - V_BUS jumper not fitted * - MASTER_EN jumper not fitted * - LIN_EN jumper fitted * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed * frequency * * * Mode transition to LPU_STOP is executed. CAN_0 is configured to wake up from *  LPU_STOP to LPU_RUN using message with standard IDE = 0 as a wake up *  preselected matching criteria. After wake up from LPU_STOP, user *  LED1 is blinking.   * * Modified files: mem.ld, sections.ld, startup.s, added file z2_restart.s * * * ------------------------------------------------------------------------------ * Test HW:         MPC5748G-324DS, MPC574xG Motherboard * MCU:             PPC5748GMMN6A 1N81M * Fsys:            PLL0 160MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  Default * * * ********************************************************************************

Detailed Description:                      This config tool simplifies DCF records calculation for MPC5777C device.                 Look at HowToUse sheet for simple guideline, then work with DCF sheet                 Notes: - Macros have to be enabled!       - Programming more than 104 DCF records on Cut1.0b will result in incorrect device operation (FCCU faults, SSCM[CER] bit set, etc)       BR, Petr

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit ECC * error in internal FLASH (user must choose it in the option at the end of main * function). * ECC error is injected by reading of pre-defined patterns in UTEST area at * addresses 0x00400040 and 0x00400060. * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 0 and * displays results into terminal window by interrupt service routine. Analog * input AN[0] requires external connection to converted voltage (potentiometer). * ------------------------------------------------------------------------------ * Test HW:        MPC5554EVB * MCU:            MPC5554MVR132 * Fsys:           132/112/80/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: USER_DEV pin RV2(i.e. pin8) -> pin B7 on I/O header ring *                 (potentiometer RV2 to analog input AN[0])   * ********************************************************************************

This document summarizes simple I2C driver implementation for MPC5xxx devices. The code follows Reference Manual's Flow-Chart of Typical I2C Interrupt Routine.

External Bus Interface FAQs related to MPC55xx and MPC56xx MCUs Preliminary version

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. This is defined by BRS macro. * Baudrate during arbitration phase is set to 500kbps, during data phase 1Mpbs * because of PHY used on the EVB. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, ISR is used to read new message. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. *   * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

This document describes how to use Lauterbach FCCU (fault collection and control unit) periphery extension for MPC57xx devices. It is expected that user has deep knowledge on FCCU mechanisms in order to effectively use this extension. This scripting tool consist of 136 scripts for Lauterbach debugger. It helps user to quickly debug micro without need of reference manual. Here is and example of windows that user can use (detailed description can be found in user guide):

This session will explain how Freescale can enable customers to develop 76-81 GHz short and long range radar applications using the MPC577xK MCU, it will explain the concepts of the radar algorithms, including practical aspects such as SDADC or MIPI CSI sampling, Chirp Generation, Data Compression, R,V FFT, Detection and Tracking algorithms, and the benefits of the new Freescale IP that can allow them to improve their system resolution and accuracy. In this session customers will take away a detailed understanding of how to develop fast modulation radar systems using the MPC577xK MCU including the BOM cost advantages it also brings.