RAM and ECC

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RAM and ECC

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jabitbe2_jcplc
Contributor I

I'm developing on the MCXN947.

Right now, my SRAM starts at 0x20000000 and has a size of 0x50000 (which is 320KB). Part of the RAM is dedicate to the ECC. But I need more RAM. Since I'm not planning on using the ECC, would it be possible to disable the ECC and repurpose the RAM banks that are allocated for it into my SRAM? 

Thanks!

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ZhangJennie
NXP TechSupport
NXP TechSupport

Hi @jabitbe2_jcplc 

If you don't need ECC, you can disable ECC to have  more SRAM used for ECC as regular SRAM, which will increase the available memory. 

All SRAM blocks (except RAMA) ECC bits are located in .SRAMG and SRAMH.  But if you disable ECC, they free up for general use. see below extracted from RM:

ZhangJennie_1-1753345636818.png

To do it, we need to configure SYSCON_ECC_ENABLE_CTRL register. Note that ECC is enabled by default for RAMB and RAMX on ECC-supported parts, but you can turn it off via this register. 

ZhangJennie_0-1753345449594.png

Just make sure to follow the specified sequence when setting the register bits to avoid issues. see below I extracted from RM

ZhangJennie_3-1753345876005.png

For more, see MCXNx4xRM, chapter 4 Memory.

Hope this will help you.

 

Jun Zhang

 

 

 

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398 次查看
ZhangJennie
NXP TechSupport
NXP TechSupport

Hi @jabitbe2_jcplc 

If you don't need ECC, you can disable ECC to have  more SRAM used for ECC as regular SRAM, which will increase the available memory. 

All SRAM blocks (except RAMA) ECC bits are located in .SRAMG and SRAMH.  But if you disable ECC, they free up for general use. see below extracted from RM:

ZhangJennie_1-1753345636818.png

To do it, we need to configure SYSCON_ECC_ENABLE_CTRL register. Note that ECC is enabled by default for RAMB and RAMX on ECC-supported parts, but you can turn it off via this register. 

ZhangJennie_0-1753345449594.png

Just make sure to follow the specified sequence when setting the register bits to avoid issues. see below I extracted from RM

ZhangJennie_3-1753345876005.png

For more, see MCXNx4xRM, chapter 4 Memory.

Hope this will help you.

 

Jun Zhang

 

 

 

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