Does LS1024A's DDR3 controller support write leveling?

[chenechun]

       Does LS1024A's DDR3 controller support write leveling?When routing the address and command traces,can we use fly-by topology?We find that T-type topology is used in the LS1024ARDB.

        Another question, where can we download the LS1024ARM(reference manual) ?

[Bulat]

Yes, write leveling is supported.

LS1024A is a regular NXP processor as many others, there is no document called LS1024ARM (reference manual). All available documentation can be found on the product page:

QorIQ® Layerscape 1024A | NXP 

Regards,

Bulat

[chenechun]

Thank you for your reply.As we know, there is a document called reference manual for many other NXP processor models.We can find information such as memory map, register description in the reference manual. But LS1024A only provides us a document called data sheet which doesn't have more detailed information.