External SRAM-like Bus Performance Limit due to Internal Bus Latency

[aivchenko]

Does Layerscape architecture like LS1028A or LS1046A have the same limitations on the external parallel bus?

[Pavel]

The IFC controller is used for connection to NOR or SRAM memory.

This IFC controller supports burst size up to 256 bytes.

Usually qDMA is used for data transfers from memory to memory.

Have a great day,
Pavel Chubakov

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