In the LS1028ARDB, SPI is not enable, some customers need to enable this interface to debug their device and some customer maybe enable this device but the SPI sequence would be some uncertain error which will delay their plan. In this documents, will introduce how to enable the SPI3 on the LS1028ARDB, and use a SPI tools in the LSDK to help customer debug their SPI device in the initial stages of debugging.

Compile kernel in the ls-5.15.71-2.2.0_distro In the LLDPUG_RevL5.15.71-2.2.0, it seems when do some reconfiguration in the kernel, rootfs should be repack to finish the change. Here will generate kernel without repack the roofts in the Linux host machine just compile the kernel.

The u-boot in SDK2.0 has a bug on SGMII2.5 support. Need to add the patch.

Follow these steps to update DPAA2 MC firmware and DPC images in QSPI flash, if you are booting LS1088ARDB from the QSPI flash memory.  qixis_reset boots the board from QSPI flash0 (aka bank0) and qixis_reset altbank boots the board from QSPI flash1 (aka bank4). “sf probe 0:1” means that the alternate bank will be written to. So if you boot from flash0, then enter sf probe 0:1, the commands that follow will program flash1. Prerequisites Linux machine. It is recommended to install Ubuntu 18.04 on the Linux machine. Obtaining MC firmware Download the prebuilt MC firmware image from the git repository: https://github.com/NXP/qoriq-mc-binary/tree/integration/ls1088a Obtaining DPC image Clone mc-utils repository and compile the DPC image. git clone https://source.codeaurora.org/external/qoriq/qoriq-components/mc-utils cd mc-utils/ git checkout LSDK-18.09 make -C config/ The compiled dpc.0x1D-0x0D.dtb is available at /mc-utils/config/ls1088a/RDB/. Flash MC firmware image on LS1088ARDB QSPI flash In U-Boot, boot from flash0, program flash1:  

LS1043ARDB version updated because we replaced the Nand Flash with different page size one as the old one is obsolete. Version update information FA version Nand flash program by CodeWarrior Nand Flash firmware bring up files Boot Mode setting

Issue description. The CodeWarrior ®  TAP enables target system debugging via a standard debug port (usually JTAG) while connected to a developer's workstation via Ethernet or USB. This the hardware debug tool(JTAG debug tool) to debug the DN MPU. You could find the tool from below link https://www.nxp.com/design/design-center/development-boards-and-designs/CW_TAP To debug the Layerscape MPU, should select CWH-CTP-BASE-HE and CWH-CTP-CTX10-YE In fact, the CWH-CTP-CTX10-YE will adapt the different signal definition, one connector will be insert to the CWH-CTP-BASE-HE, and another one(totally 10 pins) will be used to debug the Layerscape MPU. You could find the definition of the JTAG connector(CWH-CTP-CTX10-YE, 10pins) on the Layerscape board. Pin 10 (SRST)is the signal of this documents to should add workaround.     In the CodeWarrior TAP Probe User Guide, the SRST(SRST_B) is Open-drain. So the voltage of this signal should be decided by the pull-up voltage connect to it. See the schematics part below, pin 10 (JTAG_RST_B) should be 1.8V, but in fact it’s not.   The test signal will be exceed 1.8V to about 2.6V.   If you connect this pin directly to the Layerscape MPU, it will violate the SPEC of the VIN. Workaround. Workaround for the user would be to use an external circuit (level shifter/limiter) for the affected signal(s). level-shifter/limiter CWTAP <=> probe tip <=> (level-shifter/limiter) <=> target Please refer to FRWYLS1046A-PA,  use the AND gate 74AUP1G11GW similar components which the Overvoltage tolerant inputs to 3.6 V.     Logic Device Customer could also refer to LS1046ARDB CPLD LCMXO1200C-3FTN256C and LX2160ARDB CPLD EPM2210F256C5N, even the CPLD IO Voltage is 1.8V, no issue with 2.6V input on 1.8V IO ports.