Unexpected output using FIOSET and FIOCLR

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Unexpected output using FIOSET and FIOCLR

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perdrix
Contributor II

I have the following code:

	LPC_GPIO0->FIODIR |= (1<<2);	// P0.2 is output
	LPC_GPIO0->FIODIR |= (1<<3);	// P0.3 is output
	LPC_GPIO0->FIODIR |= (1<<23);	// P0.23 is output
	LPC_GPIO0->FIODIR |= (1<<24);	// P0.24 is output
	LPC_GPIO0->FIODIR |= (1<<25);	// P0.25 is output
	LPC_GPIO0->FIODIR |= (1<<26);	// P0.26 is output

	LPC_GPIO0->FIOCLR = ((1<<2) | (1<<3) | (1<<24) | (1<<25));	// Set PGC and PGD pins low
	LPC_GPIO0->FIOSET = ((1<<23) | (1<<26));	// Set MCLR pins high

This is the output I get using a logic analyser attached to the port pins

perdrix_0-1691230146884.png

I never asked for P0.23 and P0.26 to go low so why did they do so?

Puzzled, David

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perdrix
Contributor II

Anyone?

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

Can you tell us the part number you are using?

BTW, if you write the GPIO output data register directly instead of writing the FIOSET and FIOCLR register, what is the result?

BR

XiangJun Rong

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perdrix
Contributor II

I'm using an LPC1768

>if you write the GPIO output data register directly

Do you mean using FIOPIN?

David

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

LPC_GPIO0->FIOCLR = ((1<<2) | (1<<3) | (1<<24) | (1<<25));	

 

If you write the it with

LPC_GPIO0->FIOCLR = 0x0300000C;	

Is it okay?

If it is not, pls try to write the PIOPIN register.

BTW, pls try to write the mask register as zero before you write the FIOCLR

BR

XiangJun Rong

 

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perdrix
Contributor II

I already checked the assembler code and value appears to be set correctly:

0x00000550 210C      MOVS     r1,#0x0C
0x00000552 F2C03100  MOVT     r1,#0x300
   133:         LPC_GPIO0->FIOCLR = ((1<<2) | (1<<3) | (1<<24) | (1<<25));      // Set PGC and PGD pins low 
0x00000556 61E1      STR      r1,[r4,#0x1C]

David

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

If you toggle the GPIO in a forever loop and check if

for(;;)
{
LPC_GPIO0->FIOCLR = ((1<<2) | (1<<3) | (1<<24) | (1<<25));	// Set PGC and PGD pins low
	LPC_GPIO0->FIOSET = ((1<<2) | (1<<3) | (1<<23) | (1<<24)|(1<<25) | (1<<26));	// Set MCLR pins high
}
then check if the P0.23 and P0.26 pins toggle or not.
The second test is to write the FIOPIN register directly.
Hope it can help you.
BR
XiangJun rong

 

 

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perdrix
Contributor II

Hmmm that produces the following output:

perdrix_0-1691569786045.png

So P0.23 and P0.26 don't toggle - its almost as if the setting of the pins to output has forced them low and after that all behaves as expected...

Removing the FIOSET and FIOCLR settings does in fact show that they are forced low when they are set to output mode.

Is there any way that can be controlled by a user program or is that fixed behaviour?

Thanks, David

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

Good news, the GPIO pins toggle as you expected.

After you write the GPIO direction register, for the first execution of the following instruction

LPC_GPIO0->FIOCLR = ((1<<2) | (1<<3) | (1<<24) | (1<<25));	

It appears that all the port pins which are configured as GPIO output will response with the default FIOPIN register value, which leads to the problem.

If you do want to get deterministic pin logic, pls write the FIOPIN register value before you configure the GPIO direction register.

Hope it can help you

BR

XiangJun Rong

 

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