SJA1105Q-EVB

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Hello, in the SJA1105Q-EVB evaluation board, the 3.3V enable pin VREG_EN can be controlled as shown in the figure. What is the process and principle between the control by the LPC1788FET208 main chip pin MCU_VREG_INH and the control by the J9 jumper?

[Alice_Yang · Accepted solution]

Hello @哈哈哈哈哈 

On the SJA1105Q‑EVB, the 3.3 V power enable signal (VREG_EN) is typically controlled through two paths:

1. A control signal from the MCU (LPC1788), MCU_VREG_INH.
2. A hardware override via the J9 jumper, which can directly force VREG_EN on or off.
   When J9 is used, it bypasses the MCU control path.

Thank you.

BR

Alice

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If J9 pins 1 and 2 are shorted, control comes from the PHY, meaning the MAC will also lose power. How can it be awakened then?