OTP definition mismatch LPC54608

[manderson107]

I am dealing with a mismatch between the OTP bank 3 register 0 definitions for disabling JTAG/SWD between documentation and the SDK...

SDK_2.11.1_LPC54608J512_base.tar.gz devices/LPC54608/LPC54608.h defines a JTAG disable in bit 31

UM10912 LPC546xx user manual  section 46 defines SWD_DISABLE_L and SWD_DISABLE_H on bits 3 and 10

Which one is the correct way to disable access to the device via debugger?  Obviously trial and error when blowing fuses in the OTP area is not a good approach to figuring out which one is real.  So I would appreciate a clarfication here.

Thanks,
Maury

[manderson107]

ok.  But my initial question still stands.  Why are these not defined in the OTPC_ECRP bit shift/mask macros in LPC54608.h

[ZhangJennie · Accepted solution]

I have reported the header file problem to SDK team. It should be fixed in SDK2.13.0.

Thanks for bringing the problem to our attention.

BR

Jun Zhang

[ZhangJennie]

Hi

SWD access is decided by both FLASH ECRP and OTP ECRP

Here OTP ECRP (bit3 and bit10) is always set with higher priority than FLASH ECRP!

For detail, please see this article.
https://community.nxp.com/t5/LPC-Microcontrollers-Knowledge/LPC546xx-Understanding-ECRP/ta-p/1375263

Hope this helps.

Jun Zhang