I'm using a LPCXpresso54102 board and I'm trying to enter DEEP_SLEEP mode and wake up by I2C slave interrupt. I've followed the instructions in the manual (UM108050, section 25.4.3.2) and done all the steps in the required order. Anyway, no matter what order I try, I don't manage to wake up on I2C. Code works well if I don't sleep.
Any ides of what I'm doing wrong. See the code below:
#define MK_BRIDGE_I2C_PORT LPC_I2C2
#define MK_BRIDGE_I2C_INTHAND I2C2_IRQHandler
#define MK_BRIDGE_IRQNUM I2C2_IRQn
#define MK_BRIDGE_WAKEUP_SRC SYSCON_STARTER_I2C2
#define MK_BRIDGE_I2C_SCL_PIN 27
#define MK_BRIDGE_I2C_SDA_PIN 28
#define MK_BRIDGE_I2C_SCL_FN IOCON_FUNC1
#define MK_BRIDGE_I2C_SDA_FN IOCON_FUNC1
#define MK_BRIDGE_I2C_SLVADD 0x29
#define MK_BRIDGE_I2C_CLK_DIVIDER (2)
#define MK_BRIDGE_I2C_SPEED NRF_TWI_FREQ_100K
int main(void)
{
Board_Init();
NVIC_EnableIRQ(MK_BRIDGE_IRQNUM);
Chip_SYSCON_EnableWakeup(MK_BRIDGE_WAKEUP_SRC);
/* Enable the I2C controller */
Chip_I2C_Init(MK_BRIDGE_I2C_PORT);
Chip_I2CS_Enable(MK_BRIDGE_I2C_PORT);
/* Initialize I2C pins */
Chip_IOCON_PinMuxSet(LPC_IOCON, MK_BRIDGE_I2C_SCL_PORT,
MK_BRIDGE_I2C_SCL_PIN,
(MK_BRIDGE_I2C_SCL_FN | IOCON_DIGITAL_EN));
Chip_IOCON_PinMuxSet(LPC_IOCON,
MK_BRIDGE_I2C_SDA_PORT,
MK_BRIDGE_I2C_SDA_PIN, (MK_BRIDGE_I2C_SDA_FN | IOCON_DIGITAL_EN));
/* Setup clock rate for I2C */ //JH: check if we need that
Chip_I2C_SetClockDiv(MK_BRIDGE_I2C_PORT, MK_BRIDGE_I2C_CLK_DIVIDER);
/* Slave address on index 0 */
Chip_I2CS_SetSlaveAddr(MK_BRIDGE_I2C_PORT, 0, MK_BRIDGE_I2C_SLVADD);
/* Clear interrupt status and enable slave interrupts */
Chip_I2CS_ClearStatus(MK_BRIDGE_I2C_PORT, I2C_STAT_SLVDESEL);
Chip_I2C_EnableInt(MK_BRIDGE_I2C_PORT, I2C_INTENSET_SLVPENDING | I2C_INTENSET_SLVDESEL);
while(1) {
for(int j = 0; j < 5; j ++) {
for (int i = 0; i < 100000;i++);
Board_LED_Set(1, 1);
for (int i = 0; i < 100000;i++);
Board_LED_Set(1, 0);
}
Chip_POWER_EnterPowerMode(
POWER_DEEP_SLEEP,
SYSCON_PDRUNCFG_PD_WDT_OSC |
SYSCON_PDRUNCFG_PD_SRAM0A |
SYSCON_PDRUNCFG_PD_SRAM0B |
SYSCON_PDRUNCFG_PD_SRAM1 |
SYSCON_PDRUNCFG_PD_SRAM2 |
SYSCON_PDRUNCFG_PD_32K_OSC|
SYSCON_PDRUNCFG_PD_BOD_RST|
SYSCON_PDRUNCFG_PD_BOD_INTR);
}}