The datasheet of the LPC1756 is mentioning using the CLKOUT (P1.27) to calibrate the RTC.
The LPC1756 does not have P1.27 in the PIN description. Is there another pin available to multiplex this feature to?
Hi,
You are right, for the LPC175x family, all the LPC175x MCU are 80 pins package, while the LPC176x family are 100 package. The LPC176x family have the P1[27]/CLKOUT pin, but the LPC175x do not have P1[27]/CLKOUT pin.
I suppose this may be a workaround, the following fig is the clock of LPC175x, you can use the rtc_clk as the PLL input, for example multiply the rtc_clk with a number N, the PLL clock PLLCLK will be rtc_clck*N. Then the CCLK frequency will be rtc_clk*N. You can use for example I2S as a master, the I2S bit clock can be from the pclk1, the I2S bit clock can be configures as cclk/N or rtc_clk with an internal divider, because the bit clock of I2S is continuous, so you can calibrate the rtc_clk.
Hope it can help you
BR
XiangJun Rong
Hi,
You are right, for the LPC175x family, all the LPC175x MCU are 80 pins package, while the LPC176x family are 100 package. The LPC176x family have the P1[27]/CLKOUT pin, but the LPC175x do not have P1[27]/CLKOUT pin.
I suppose this may be a workaround, the following fig is the clock of LPC175x, you can use the rtc_clk as the PLL input, for example multiply the rtc_clk with a number N, the PLL clock PLLCLK will be rtc_clck*N. Then the CCLK frequency will be rtc_clk*N. You can use for example I2S as a master, the I2S bit clock can be from the pclk1, the I2S bit clock can be configures as cclk/N or rtc_clk with an internal divider, because the bit clock of I2S is continuous, so you can calibrate the rtc_clk.
Hope it can help you
BR
XiangJun Rong
