LPCXpresso804 board has a on-board debugger developed with LPC11U35. Old batches of the board uses the old firmware for LPC11U35 debugger. The old firmware has some issues such as that when you send a string through the debug COM port the LPC804 only can receive the first byte. The solution is easy. We can download the newest firmware for LPC11U35 and update the firmware for LPC11U35. Download the fimware. The firmware and driver can be download from this link. Update the firmware.(Details can be found in UM11083: User Manual for LPCXpresso804 Board) Hold down the reset button and keep it held down while applying power to the board. Release reset. Using File Explorer (or equivalent on Mac/Linux platforms), look at the available drives on your system. A device called CRP_DISABLED will appear. Delete the firmware.bin file on the CRP_DISABLED drive. Drag and drop the firmware.bin file you downloaded from nxp.com on to the CRP_DISABLED drive. Re-power the board. The board should now enumerate on your system - allow 20-30 seconds for this to complete.

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When we use LPC55Sxx PRINCE feature, we need enable PRINCE sub-region “crypto” by setting SR_ENABLE register. If we “crypto” enable discontinuous sub-regions and erase part of them, we may find we can’t erase/read/write other “crypto” sub-regions any more. This article will discuss how to resolve this phenomenon.           Figure 1         Testing Steps According to LPC55Sxx UM, each PRINCE region has its SR_ENABLEx register. This register enables PRINCE encryption and decryption of data for each sub-region of crypto region 0. Each bit in this field enables a sub-region of crypto region 0 at offset 8kB*n, where n is the bit number.  For example, when we set SR_ENABLE0=0X00000005, PRINCE region 0 sub-region 1 and sub-region 3 are set as encryption region. When read data out from these sub-regions, PRINCE will decrypt the data automatically.   Now we will test discontinuous sub-region erase/read/write. Board: LPC55S16-EVK IDE: Keil MDK v5.29 Step 1: PRINCE initialization: Enable PRINCE region 0 and two discontinuous sub-regions; generate key, IV code; enable crypto. //set SR_ENABLE，SR_ENABLE=0X28000000,enable sub-regions(0x30000-0x32000,0x34000-0x36000) crypto。 status=PRINCE_SetRegionSREnable(PRINCE(prince_region_t)region0,0X28000000); //select PRINCE crypto for region0 PRINCE_SetRegionBaseAddress(PRINCE_Type*base,prince_region_tregion0,uint32_t0X0) //generate PRINCE region0 crypto key Status=FFR_KeystoreGetKC(&flashInstance,&keyCode[0],kFFR_KeyTypePrinceRegion0); status=PUF_GetHwKey(PUF,keyCode,sizeof(keyCode),kPUF_KeySlot2, rand()); //generate PRINCE region0 crypto IV_code status=PRINCE_GenNewIV(kPRINCE_Region0,&prince_iv_code[0],true,&flashInstance) //load IV code to PRINCE status=PRINCE_LoadIV(kPRINCE_Region0,&prince_iv_code[0]) //enable PRINCE encryption PRINCE_EncryptEnable(PRINCE)   Step 2: Select two discontinuous sub-regions ( 0x30000-0x32000,0x34000-0x36000). Erase one of them (0x30000-0x32000), then write data to this sub-region. Output: Erasing and Writing are all successful. See Figure 2. //Erase 0x30000-0x32000 sub-region status=PRINCE_FlashEraseWithChecker(&flashInstance,0x30000,0x2000,kFLASH_ApiEraseKey); //Write 0x30000-0x32000 sub-region status=PRINCE_FlashProgramWithChecker(&flashInstance,0x30000,(uint8_t *)prince_iv_code,0x2000);   Step 3: Erase and Write the other sub-region ( 0x34000-0x36000 ) Output: Erasing and Writing are failed. See Figure 2. //Erasing 0x34000-0x36000 sub-region status=PRINCE_FlashEraseWithChecker(&flashInstance,0x34000, 0x2000,kFLASH_ApiEraseKey); //Write 0x34000-0x36000 sub-region status=PRINCE_FlashProgramWithChecker(&flashInstance,0x34000, (uint8_t *)prince_iv_code,0x2000); Error Analysis According to UM11126（49.16.1 Functional details）, each crypto region has its own SKEY and IV code. SKEY and IV are used together by the PRINCE when encrypting or decrypting the data in the sub-regions of crypto region. For Instance, For PRINCE region1, each time after we execute erasing operation, new Skey1 and IV1 are generated, thus when executing erase/read/write operation to another sub-region, the old IV1 and new IV1 don’t match, which causes PRINCE can’t decrypt correctly.   Suggestion We suggest user using SR_ENABLE to set continuous crypto sub-regions. When erasing operation is needed, erasing all the crypto sub-regions together, avoid erasing part of the sub-regions. One sub-region size is 8K, make sure the erasing/writing address 8K aligned.   Thanks for the suggestion from johnwu‌

This content was originally contributed to lpcware.com by Massimo Manca Example application for the "LPC4300 Getting started Kit" to learn and to use the multi processor communication and the newest peripherals of LPC43xx MCU family. System resources used and assignment to the cores: The Cortex-M4 core handles the application logic, manages the 4 touch keys and 4 leds (via the PCA9502 I2C 8 bit I7O expander), the lcd display and the real time clock. The Cortex-M0 core is dedicated to the printer management using the RS232 on board interface (in near future SCT and SGPIO will be used to interface a thermal printing head). The cores communicates using inter processor communication mechanisms minimizing the data passed from M4 to M0 and providing a simple security mechanism.

[中文翻译版] 见附件 原文链接： https://community.nxp.com/docs/DOC-343506

  Contents 1.Problem description      2.  Reason analysis      3. Solutions    3.1   SRAM power down problem solution    3.2   Alarm timer interrupt enable problem solution   3.3   Downcounter register write problem solution    4. Verification Considerations   1.     Problem description When LPC43xx series runs the LPCOpen low-power demo “misc_pmc_states”, the two modes of power down and deep power down cannot successfully wake up through the Alarm Timer. This paper analyzes the series of problems and provides corresponding solutions. The same problem and solution exists for waking up via RTC. 2.     Reason analysis The reasons for wake-up failure include the following three aspects. - SRAM power down problem: In the power down mode of LPC43xx series, only the 8K SRAM is not powered down, and other SRAMs are powered down. After waking up from power down mode, the program continues to execute backwards, not reset. Therefore, it should be ensured that when entering power down, the data is in the 8K SRAM that does not lose power, so after wake up, it can continue running. - Alarm timer interrupt enable problem: The LPC43xx  Alarm timer interrupt enable need a while to take effect. If it is not successfully enabled before entering low power, it cannot wake up from low power mode. - Downcounter register problem: In LPC43xx series, in order to ensure the wake-up at the specified time, it is necessary to judge that the set value is successfully written into the Downcounter register. The table of reasons for wake-up failures in power down and deep power down modes is summarized as follows:   3.     Solutions For power down wake-up failure, it needs to be solved according to three problems. There is no data loss problem for deep power down wakeup. Because after waking up from deep power down mode, the program is reset and executed again, and the previous data is not needed. So the solution skips the first and only needs 3.2 and 3.3. 3.1  SRAM power down problem solution As shown in the manual, only 8kB local SRAM will not lose power in LPC43xx series Power-down mode. Note: Chips with and without internal flash have different 8K SRAM address ranges.   For LPC4330/LPC4350/LPC4370 series products without internal flash, the 8K SRAM address range is 0x10090000– 0x10092000 (8KB). The address range of chips with internal flash such as LPC4337/LPC4367 is 0x10088000 – 0x1008A000 (8KB).   Placing data in this 8K SRAM area can solve the problem of lost data. Taking LPC4350 as an example, the setting method in MCUXpressoIDE is as follows: Find the following interface according to Project \ Properties \ C\C++ Build\MCU settings path, define this 8K SRAM separately, the address is 0x10090000, and the size is set to 0x2000. At this point, the setting of the power loss problem in the SRAM area is completed. 3.2  Alarm timer interrupt enable problem solution To ensure that the Alarm timer interrupt is enabled, add a while loop poll after it until it is successfully enabled. Enter the function in the src\pmc_states.c path. And add while((LPC_ATIMER->ENABLE& 0x01) != 0x01){} after the Chip_ATIMER_IntEnable(LPC_ATIMER); function statement in the corresponding case mode.   3.3  Downcounter register write problem solution The solution to this problem is similar to 3.2. Still enter the function with the src\pmc_states.c path, and find LPC_ATIMER->DOWNCOUNTER= RTC_ALARM_TIME*1000 in the case of the corresponding mode (consistent with the 3.2 position). Add a while statement after it: while(LPC_ATIMER->DOWNCOUNTER != RTC_ALARM_TIME*1000); As shown below.   4.     Verification Considerations When there is no internal flash development board for testing (eg: LPC4370, LPC4350…), such as the Hitex LPC4350Evaluation board, it is necessary to configure the startup as external flash startup. The reference picture is as follows.   When starting, you need to set the pins P2_9, P2_8, P1_2, P1-1 to the form of low, low and high, and start in the form of SPIFI. Jumper settings are shown in the figure.  

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        In recently, NXP released a new sub-series: LPC80x which contains two kinds: LPC802 and LPC804 now, they have a variety of package types for choose and the LPC804 seems like the advanced version to LPC802. For details, please refer to these two articles: 《小巧‘零’珑的MCU：LPC80X面面观》 《LPC800系列选型指南》        Below are block diagrams of LPC802 and LPC804. We can find the difference easily after comparing them. Fig1 LPC802 system block diagram Fig2 LPC804 system block diagram        According to the above two figures, we can find that LPC804 has the capacitive touch interface, programmable logic unit (PLU), 10-bit DAC output, and an I2C interface. But these peripherals are not supported in the LPC802. In further, LPC804 has two times as much memory as LPC802 does.Especially, the capacitive touch interface provides hardware support for LPC804 to design the complex HMI implemented.        In the coming section, I'd like to illustrate the problem capacitive touch demo and share some experience to overcome it. Capacitive Touch Demo Testing 1. Evaluation board (OM40001) Fig3 LPCXpresso804 Develpment Kit        2. Demo code        CapTouch_5ch demo is from Code Bundle (supports Keil, IAR, and MCUXpresso), after reset, all the 5 LEDs would be On and Off one by one and flash together. Please do not touch the pads during this period. After all the LEDs are silent, touch any pad and the responding LED will be on until your finger moves away. Meanwhile, run the Freemaster project to monitor the sensing value in runtime. Fig4 Capacitive Touch Shield Fig5 FreeMASTER monitor the sensing value          3. Testing summary         In general, the testing result is not very good, for instance, when touching S4 and S3, LED D1~D5 may be lighted arbitrarily, even the S1 and S2 which have the best performance,  the responding LED usually be on when touching them, sometimes other LEDs would response the touching event.         Combining with the observation of FreeMaster, it can get the conclusion that the discrimination of these touchpads is not enough to distinguish each other.          4. Workaroud         According to the feedback from the AE co-worker, the discrimination performance of the touchpad is mainly determined by the PCB design and the power supply source. Obviously, the touchpad is impossible to be modified, so we should consider eliminating the power supply's noise to improve the performance.          I tried these three power source for supply. Using the USB port of the notebook, meanwhile, the notebook is supplied by 220 V, 50 Hz Using the USB port of the notebook Using mobile power       After several rounds of testing, it illustrates that demo code can work well when using mobile power to supply, as the mobile power is clean enough and the noise is the smallest.       Note: Slowing the FCLK can extend the scan period for a channel (more energy is released through YL for each recharge cycle), then increase the discriminability performance.  mobile power supply

When you are the first time to debug LPC55S69, please read below document and double check your IDE, SDK and EVK version is correct. Usually, we prefer use the latest IDE, SDK and EVK boards. Important updates when using LPCXpresso55S69 Revision A2 boards and 1B silicon  [Problem Description] When you use IAR 8.32 to debug LPC55S69 '1B' silicon, the IDE will remind you "The debugging session could not be started", like below picture show: The reason of this failure is that IAR 8.32's LPC55S69 chip configuration files only support revision '0A' silicon, not '1B'. We strongly recommend customer download and use IAR 8.40.2 or latest version. The IAR IDE start support LPC55S68 '1B' silicon from 8.40.2. [Solution] If you have some reasons that must use IAR 8.32, you can download attached zip file. This zip file like a patch, include the IAR LPC55S69 '1B' support files. Un-zip this file and merge the same files under IAR installed path :IAR\arm\config\flashloader\NXP Then the IAR can support '1B' silicons. [How to identify LPC55(S)6x chip silicon versions] On the top-side marking code, there is '1B'  charactors at the end of mark strings. See below two pictures, the left one is '1B' version chips.                      LPC55(S)6x ver '1B'                                                               LPC55(S)6x ver '0A'                   

I updated the design for the Mini-Monkey and used PCB:NG for fabrication.

This is an example of how to use the CTimer to trigger the LPADC conversion in the LPC55s28. I attached the example in MCUXpresso.    

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For LPC55(S)1x/2x/6x users, please update your fsl_power_lib to SDK2.8.2. The previous SDK(2.6.x and 2.7.x)'s power library have two known function bugs,  1. FRO trim value can not be recovery correctly after wakeup from deep-sleep / power-down / deep power-down.    -- this means the 12MHz FRO frequency is different for after boot-process(11.99 MHz for example) and wakeup from low-power modes(11.89MHz for example).     -- The reason is the FRO trim value not recovery after wakeup.  2. Cap-bank value can not be set correctly by use power lib capbank trim API.    -- This is a software bug which fixed in SDK2.8.2 already. Just replacement the power_lib library file should be workable for most of customers. the API should be compatible. Thank you! Magicoe

#emc‌ #buffer‌ #flush‌

lpc‌ feature‌ LCD‌ Attached doc is the LPC MCU Serial LCD controller feature introduction and application

Abstract This paper discusses our approach to crypto acceleration and asset protection using novel techniques that help bring high levels of security to low-cost microcontrollers with minimal power and area penalty. CASPER, our asymmetric cryptography acceleration engine, aims to optimize crypto algorithm execution (e.g., RSA, ECC). It is built on a hardware-software partitioning scheme where software functions map asymmetric crypto functions to the hardware modules of the accelerator, delivering sufficient flexibility to software routines to enable mapping of new algorithms. Further efficiency is achieved by making use of the co-processor interface on the Arm® Cortex®-M33 core. Important assets such as keys, proprietary and/or licensed application software are protected against side-channel analysis or cloning using SRAM PUF and PRINCE. SRAM PUF technology enables secure storage of root-of-trust keys and user keys by exploiting the deep sub-micron process technology variations. PRINCE is a low-latency lightweight cryptography algorithm implementation in hardware that allows encrypted non-volatile storage and real-time, latency-free decryption of the execution code. Read More >