processor expert bug - FlexBus ALE is taking more than one clock

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processor expert bug - FlexBus ALE is taking more than one clock

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zohargolan
Contributor III

Hi,

I am trying to setup Flexbus using processor expert and I the ALE size is multiple clocks.

the device I am using is mk20fx512vmd12

and I am using Kinetis Design Studio Version: 2.0.0 Eclipse Version: Kepler (4.3.2)

Here is my flexbus init from cpu.c

/* SIM_SCGC7: FLEXBUS=1 */

  SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;

        /* Initialization of the ExternalBus module */

  /* SIM_SOPT2: FBSL=0 */

  SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_FBSL(0x03));

  /* FB_CSAR0: BA=0xA000,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

  FB_CSAR0 = FB_CSAR_BA(0xA000);

  /* FB_CSCR0: SWS=0,??=0,??=0,SWSEN=0,EXTS=1,ASET=0,RDAH=0,WRAH=0,WS=0,BLS=1,AA=1,PS=1,BEM=0,BSTR=0,BSTW=0,??=0,??=0,??=0 */

  FB_CSCR0 = FB_CSCR_SWS(0x00) |

             FB_CSCR_EXTS_MASK |

             FB_CSCR_ASET(0x00) |

             FB_CSCR_RDAH(0x00) |

             FB_CSCR_WRAH(0x00) |

             FB_CSCR_WS(0x00) |

             FB_CSCR_BLS_MASK |

             FB_CSCR_AA_MASK |

             FB_CSCR_PS(0x01);

  /* FB_CSMR0: BAM=0x0F,??=0,??=0,??=0,??=0,??=0,??=0,??=0,WP=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,V=1 */

  FB_CSMR0 = (FB_CSMR_BAM(0x0F) | FB_CSMR_V_MASK);

  /* FB_CSMR1: V=0 */

  FB_CSMR1 &= (uint32_t)~(uint32_t)(FB_CSMR_V_MASK);

  /* FB_CSMR2: V=0 */

  FB_CSMR2 &= (uint32_t)~(uint32_t)(FB_CSMR_V_MASK);

  /* FB_CSMR3: V=0 */

  FB_CSMR3 &= (uint32_t)~(uint32_t)(FB_CSMR_V_MASK);

  /* FB_CSMR4: V=0 */

  FB_CSMR4 &= (uint32_t)~(uint32_t)(FB_CSMR_V_MASK);

  /* FB_CSMR5: V=0 */

  FB_CSMR5 &= (uint32_t)~(uint32_t)(FB_CSMR_V_MASK);

Please advise,

Best regards,

Zohar

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1 Solution
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Kan_Li
NXP TechSupport
NXP TechSupport

Hi Zohar golan,

I noticed you set EXTS=1, so that might be the root cause, you have to set it as zero to let FB_ALE just asserts for one bus clock cycle, please refer to the following for details.

sf1.png

2.png

Hope that helps,


Have a great day,
Kan

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1 Reply
524 Views
Kan_Li
NXP TechSupport
NXP TechSupport

Hi Zohar golan,

I noticed you set EXTS=1, so that might be the root cause, you have to set it as zero to let FB_ALE just asserts for one bus clock cycle, please refer to the following for details.

sf1.png

2.png

Hope that helps,


Have a great day,
Kan

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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