max DMA data rate documentation

[mjg8t]

I am looking into using DMA for a high bandwidth application and need to know the max data rate that the DMA engine can handle.  I cannot find this in the datasheet or reference manual.  I have found the max rate for 100Mhz k60 devices to be 8.7Mhz in AN4627, but what about the higher speed MCUs?  I am looking at using the MK22FN512LH12 device. 

[mjbcswitzerland · Accepted solution]

Hi

The K22FN512 , running at 120MHz core, 60MHz bus and 24MHz Flash transfers SRAM to SRAM (long words) at 225 MBytes/s using a DMA controller channel.
From Flash to SRAM is drops to 120MBytes/s.

If byte size transfers are made the speed is 1/4 this rate.

This is maximum speed when there is no other major activity taking place (only one DMA channel active at a time).

The default cross-bar arbiter policy is a fixed priority where the DMA controller has a high priority by default. If USB on the K22 is used with such transfers it is recommended to either give the DMA controller a lower priority that USB, or generally set round robin. If not, the USB master can be blocked for periods adequate for it to start losing data and USB repetitions start taking place.

Regards

Mark

http://www.utasker.com/kinetis/FRDM-K22F.html
http://www.utasker.com/kinetis/TWR-K22F120M.html
http://www.utasker.com/kinetis/BLAZE_K22.html

[Jonathan_Iglesias]

Hi mjg8t,

Hope you are doing great.

To test this, you can set-up a DMA transfer transferring a block of some data.

for instance copy some RAM buffer to another RAM location. You can measure the time required by toggling the pin at the end of the transfer or at the beginning and the end of the transfer. Or you can measure this period by the SYSTICK or other timer. Then you can calculate transfer speed for the specific cases.

The speed of the transfer may be different, for instance if you are accessing the FLASH or Peripheral Register space or external bus. Because then the data transactions are delayed by internal bus multiplexing (AHB master / slave ports).

Moreover, the speed may be affected by the priorities between the CPU and DMA controllers ( bus masters), when they want to access the same type of the memory (concurrent access). For instance the DMA must wait, causing additional delays.

Our practical measurements shown (very rough estimation) that DMA transfer spped can typically achieve

System clock / 10. It means when the System frequency = 100MHz, DMA can transfer 10Mbytes/s

Hope this helps.

Have a great day

Jonathan