Need to increase ADC Speed after ADC Calibration in MK60 Device

[nbjasani]

Hi,

   I am working on MK60DN510VMD10 device, software tool is MCUXpresso IDE, i used SDK Files. 

   As per document suggested i configure ADC before doing ADC Calibration. That configuration as follows.

  -> Reference Voltage = Vref (not Valt).

  -> Clock Source = Bus/2 (In my case Bus Clock is 50MHz).

 -> Asynchronous clock is disable.

 -> 8 Clock Divider. (According to that fADCK = 3.125MHz).

 -> Resolution is 16 Bits.

 -> High Speed, Low Power and Continuous Conversion are disable.

 -> Enable Hardware averaging with 32 Samples.

 After this configuration i do ADC Calibration. But now i need to increase fADCK to 6.25MHz after ADC Calibration. My question is, Is there any effect in Calibration after increasing ADC Clock?

Thanks

Nandish Jasani.

[Robin_Shen]

Hi Nandish Jasani,

6MHz or less having a lower frequency means that the SAR has more sample time, therefore less room to give wrong calibration values.

But the calibration results can be affected by the clock source, frequency, power and conversion speed settings, voltage reference, hardware average function, the sample time and to a much lesser extent, environment. 

Q: Is there any effect in Calibration after increasing ADC Clock?

A: yes. Please do ADC calibration with fADCK=6.25MHz.

Best Regards,

Robin

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[nbjasani]

Thanks Robin Shen, 

    I understand your point.

Best Regards,

Nandish Jasani.