There is a work-around. This is hinted in the DMA multiplexer "Chip Configuration" section of the controller's reference manual, but the manual doesn't go into detail.
If you have a PIT timer available:
1. Perform receive side setup in the same manner as for SPI0.
2. Set up the transmit side DMA on channel 0..3 depending on the PIT timer channel to be used. Select one of the always-enabled request sources in the channel configuration register, and set the TRIG bit.
3. Configure the DMA transmit descriptor for memory-to-register transfer.
4. Set the PIT timer period. The period of the timer must be a bit longer than the SPI byte transfer time so that the transmit buffer is empty when the transmit DMA channel writes the next byte. Trial and error with an oscilloscope, or calculate it...
5. Set the SPI chip select. It mayt be possible for the SPI controller to do this, I'm doing it in code.
6. Enable the receive-side DMA transfer. Nothng happens since no SPI clocks are generated.
7. Enable the transmit-side DMA transfer. Transfer occurs.
8. Negate the chip select via interrupt callback when the transfer completes.
I'm guessing something similar works using one of the flex timer channels as trigger source, but I haven't verified that.