KV5x cache and linker file

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KV5x cache and linker file

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pietrodicastri
Senior Contributor II

Good morning

I am using the TWR-KV58F220M.

I would like to see in order the cache usage and the linker file.

I read the MKV58F1M0xxx24_flash.ld and I see the 

   m_data_3 space not used at all.

   m_data_2 used only for the heap and stack

  m_data for everything.

The URM of the processor does not detail about the initialization of the cache, the Figure 2-1. is presenting the cache area as part of a block, so I suppose the 16KB + 8KB are inside the m_data and should not be used as data holder unless the cache is disabled.

in the Chapter 3 Core Overview there is a summative description of some memory area.

I do not find a clear description of what the different ram spaces are referring to.

So some simple questions are:

  1. Is the m_data area totaly freely usable for data and ram mapped code?
  2. are the m_data2 and m_data3 slower than m_data?
  3. why the linker file does not use the m_data3?
  4. If I want to choice the m_data, assumed faster for critical code and data is is possible?
  5. Should I move the .data and the .bss in the m_data2 or m_data3 for granting more space in the faster m_data?
  6. There are two section in m_data called  .ncache.init and  .ncache... What are they?

I hope I can get some answers..

Thank You

Pietro

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jingpan
NXP TechSupport
NXP TechSupport

Hi,

First of all, cache is not a part of ITCM. It is standalone. Icache is mainly for flash and dcache is mainly for OCRAM. TCM means tightly coupled memory. CPU core can access them very quickly, so they dont need cache.
1. Yes, you can use m_data freely.
2. m_data and m_data2 are almost same. M_data3 may slower than m_data and m_data2, because data accesses are performed over the AXIM interface.
3. I think this is may because some KV58/56 do not have OCRAM. And to most of the demo, m_data/m_data2 is enough.
4. Yes,  put critical code in ITCM and critical data in DTCM is sensible.
5. It's up to your case.
6. I can find this name. I guess if you don't want some data cacheable, you can use it to put the data into m_data.

Regards,

Jing

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jingpan
NXP TechSupport
NXP TechSupport

Hi,

First of all, cache is not a part of ITCM. It is standalone. Icache is mainly for flash and dcache is mainly for OCRAM. TCM means tightly coupled memory. CPU core can access them very quickly, so they dont need cache.
1. Yes, you can use m_data freely.
2. m_data and m_data2 are almost same. M_data3 may slower than m_data and m_data2, because data accesses are performed over the AXIM interface.
3. I think this is may because some KV58/56 do not have OCRAM. And to most of the demo, m_data/m_data2 is enough.
4. Yes,  put critical code in ITCM and critical data in DTCM is sensible.
5. It's up to your case.
6. I can find this name. I guess if you don't want some data cacheable, you can use it to put the data into m_data.

Regards,

Jing

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pietrodicastri
Senior Contributor II

Hei Jing Pan

That's an optimal answer. 

Thak You

Pietro

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