Greetings all,
I've been battling this for a while and not getting too far.
The problem is the KL05 receives the correct address from the master, ACKs it, then something very odd happens to the following byte. I have not been able to work out why.
A KL03 used to work perfectly in the KL05's place (using the KL05 now due to parts shortages).
The KL05 is running off the internal clock at 20Mhz, the bus clock div is 1 (also 20Mhz).
Attached is a image of the I2C signals. The address byte, and then the odd first data byte.
The pins and I2C peripheral are setup as following:
//i2c pin setup
PORTA->PCR[4] = PORT_PCR_MUX(0x02);
PORTA->PCR[3] = PORT_PCR_MUX(0x02);
//setup i2c hardware slave
CLOCK_EnableClock(kCLOCK_I2c0);
//set slave addr, no ranage
I2C0->A1 = 0x38 << 1U;
I2C0->RA = 0;
I2C0->C2 = 0;
//speed (I2C speed of master is ~315kHz)
I2C0->F = I2C_F_MULT(0) | I2C_F_ICR(6);
//glitch filter value, stop hold enable, and stop int
I2C0->FLT = I2C_FLT_FLT(0) | I2C_FLT_STOPF_MASK | I2C_FLT_STOPIE_MASK;
//reset all flags
I2C0->S = 0xFFU;
//enable slave, and slave int
I2C0->C1 = I2C_C1_IICEN_MASK | I2C_C1_IICIE_MASK;
//enable
NVIC_SetPriority(I2C0_IRQn, 1);
EnableIRQ(I2C0_IRQn);
The interrupt handler looks like:
void I2C0_IRQHandler(void)
{
//I2C IRQ handler
volatile uint8_t data = 0;
volatile uint8_t status;
bool doTransmit = false;
static bool isBusy = false;
//read flags
status = I2C_SlaveGetStatusFlags(I2C0);
//clear interrupt service flag
I2C0->S = I2C_S_IICIF_MASK;
//arbitration lost?
if (status & I2C_S_ARBL_MASK)
{
//clear ARBL
I2C0->S = I2C_S_ARBL_MASK;
//set receive mode
I2C0->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
//nothing more to do
return;
}
//check NAK
if (status & I2C_S_RXAK_MASK)
{
//set receive mode
I2C0->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
//read dummy
data = I2C0->D;
//do something?
}
else
//Check address match
if (status & I2C_S_IAAS_MASK)
{
//slave transmit, master reading from slave
isBusy = true;
if (status & I2C_S_SRW_MASK)
{
//change direction to send data
I2C0->C1 |= I2C_C1_TX_MASK;
doTransmit = true;
}
else
{
//slave receive, master writing to us
//send ack
I2C0->C1 &= ~(I2C_C1_TXAK_MASK);
//read dummy to release the bus
data = I2C0->D;
//reset inbuf
indatac = 0;
}
//do something here?
}
else
//check transfer complete flag
if (status & I2C_S_TCF_MASK)
{
if (status & I2C_S_SRW_MASK)
{
//slave transmit, master reading from slave
doTransmit = true;
}
else
{
//slave receive, master writing to slave
//ack
I2C0->C1 &= ~I2C_C1_TXAK_MASK;
//get data
data = I2C0->D;
indata[indatac++] = data;
}
}
else
{
//read dummy to release bus
data = I2C0->D;
}
//send data if there is the need
if (doTransmit)
{
//send data
if (!sendComplete)
{
I2C0->D = outdata[outdatac++];
}
else
{
//switch to receive mode
I2C0->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
//read dummy to release bus
data = I2C0->D;
}
}
//done
}
Anyone have any ideas what's going on here?
Thanks in advance.
Mark,
Thanks a lot for providing the snippet Mark.
Unfortunately implementing a very similar i2c handling int changes nothing. I still end up with the same lack of int/ack after the sent data byte.
//i2c pin setup
BOARD_INITPINS_EVE_CTP_SDA_PORT->PCR[BOARD_INITPINS_EVE_CTP_SDA_PIN] = PORT_PCR_MUX(0x02);
BOARD_INITPINS_EVE_CTP_SCL_PORT->PCR[BOARD_INITPINS_EVE_CTP_SCL_PIN] = PORT_PCR_MUX(0x02);
//i2c NVIC setup
NVIC_SetPriority(I2C0_IRQn, 1); //set i2c0 int priority
EnableIRQ(I2C0_IRQn); //enable int
//setup i2c hardware slave
CLOCK_EnableClock(kCLOCK_I2c0); //enable i2c clock
I2C0->A1 = 0x38 << 1U; //set our slave address
I2C0->RA = 0; //no addr range
I2C0->C2 = 0;
I2C0->SMB = 0; //no smbus use
//speed (I2C speed of master is ~315kHz)
I2C0->F = 0; //set speed
I2C0->S = 0xFFU; //reset all flags
I2C0->C1 = I2C_C1_IICEN_MASK; //enable i2c peripheral
I2C0->C1 |= I2C_C1_IICIE_MASK; //enable ints
I2C0->FLT = I2C_FLT_STOPIE_MASK; //enable stop cond int
int:
void I2C0_IRQHandler(void)
{
//I2C IRQ handler
volatile uint8_t data = 0;
volatile uint8_t status;
bool doTransmit = false;
//arbitration lost?
if (I2C0->S & I2C_S_ARBL_MASK)
{
//clear ARBL
I2C0->S = I2C_S_ARBL_MASK;
ARBLostCount++;
}
//check for stop flag
if (I2C0->FLT & I2C_FLT_STOPF_MASK)
{
//stop condition has been detected
I2C0->FLT = I2C_FLT_STOPF_MASK; //clear flag
I2C0->S = I2C_S_IICIF_MASK; //clear interrupt service flag
if ((I2C0->S & (I2C_S_IAAS_MASK | I2C_S_TCF_MASK)) != (I2C_S_IAAS_MASK | I2C_S_TCF_MASK))
{
//if the slave is already addressed we allow the reception handling to continue since we will have cleared the reception interrupt
return;
}
}
//clear interrupt service flag
I2C0->S = I2C_S_IICIF_MASK;
//check address match
if (I2C0->S & I2C_S_IAAS_MASK)
{
//address matched
isBusy = true;
if (I2C0->S & I2C_S_SRW_MASK)
{
//slave transmit, master reading from us
//change direction to send data
I2C0->C1 |= I2C_C1_TX_MASK;
//clear interrupt service flag
I2C0->S = I2C_S_IICIF_MASK;
//flag transmit
doTransmit = true;
}
else
{
//slave receive, master writing to us
//send ack, recv mode
//I2C0->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
I2C0->C1 = I2C_C1_IICEN_MASK | I2C_C1_IICIE_MASK;
//read dummy to release the bus
data = I2C0->D;
//reset inbuf count
indatac = 0;
}
}
else
{
//check transfer complete flag
if (I2C0->S & I2C_S_TCF_MASK)
{
if (I2C0->S & I2C_S_SRW_MASK)
{
//slave transmit, master reading from slave
doTransmit = true;
}
else
{
//slave receive, master writing to slave
//clear interrupt service flag
I2C0->S = I2C_S_IICIF_MASK;
//ack
I2C0->C1 &= ~I2C_C1_TXAK_MASK;
//get data
data = I2C0->D;
indata[indatac++] = data;
}
}
else
{
//clear interrupt service flag
I2C0->S = I2C_S_IICIF_MASK;
//read dummy to release bus
data = I2C0->D;
}
}
//send data if there is the need
if (doTransmit)
{
//send data
}
//done
(void)data;
}
At the location of the B cursor, the INT is called with IAAS and !SRW (as it should).
The INT is never triggered again after that. Nothing ever happens after the B cursor.
I've found something else interesting...
I have a variation of the fw that using blocking (non INT driven) handling of I2C0.
With I2C0->F=0, it does not work. It gives the same immediate result as the INT handling code.
With I2C0->F=69 (MULT=2 ICR=5), it does work for 4-5 I2C transactions before failing.
This is a capture of the blocking i2c handling code, with F=69.
Note the very short SDA pulses which i have circled in red (i have no idea what they are or are caused by).
